FPGA Intellectual Property
PCI Express*, Networking and Connectivity, Memory Interfaces, DSP IP, and Video IP
Announcements
Intel Support hours are Monday-Fridays, 8am-5pm PST, except Holidays. Thanks to our community members who provide support during our down time or before we get to your questions. We appreciate you!

Need Forum Guidance? Click here
Search our FPGA Knowledge Articles here.
5881 Discussions

Clearing asyncram contents

Altera_Forum
Honored Contributor II
979 Views

Just wanted to verify the following: 

 

Does the Aclr pin only clear the input and output registers on the component, and leave the contents of the memory in tact? Was just wondering about this before I go ahead and write a loop of reset code to write a 0 value to every address. The Aclr would be an easy way of clearing the memory, but I don't think that is it's intent. Can someone please verify this for me?
0 Kudos
3 Replies
Altera_Forum
Honored Contributor II
67 Views

the ram contents are not cleared 

 

only output registers/latches (not input registers) are cleared in most recent families 

 

see page 31: 

 

http://www.altera.com/literature/ug/ug_ram_rom.pdf
Altera_Forum
Honored Contributor II
67 Views

As far as I know, the aclr clears the registers (inputs/outputs/address)

Altera_Forum
Honored Contributor II
67 Views

Yeah, that's what I thought. So the only way to clear the RAM during runtime is to actually run a loop through all the addresses and write 0's to all of them. 

 

Ok. Thanks for the verification.
Reply