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Altera_Forum
Honored Contributor I
1,170 Views

Clock Assignment on (X,Y) region for DDR3 SDRAM Controller with UniPHY IP in Arria V

can anyone please help explain how does the tool go about the (x,y) coordinate of region to decide which fractional pll the clock will use to output clock to logic? 

 

I am targeting Arria V GX 896-pin device, and placing the DDR3 memory interface on Banks 3A, 3C, 3D, 4C, and 4D. 

I can't find the constraint anywhere in the SDC to lock the PLL location, but I have narrow it down to the clock pin must be connected at the pin where it has input of DLL_X4_Y0_N0/DLL_X94_Y0_N0, and the adjacent dedicated clock pin which has access to only DLL_X94_Y0_N0 won't work, in the mean time, these two clock pins both have access to the Global/Quadrant and all of the Spine <index> will lead to the following error.  

 

Hence, moving back forth between the two clock pins will get me either a successful compilation, or the transcript below. 

 

Is there a file I have overlooked that carries the pin-constraint on the PLL location for specific device family?  

 

please see transcript below (sorry for the smiley faces): 

 

 

Info (175028): The PLL LVDS output name: q_sys:u0|q_sys_mem_if_ddr3_emif_0_0002:mem_if_ddr3_emif_0|q_sys_mem_if_ddr3_emif_0_pll0:pll0|pll2_phy~PLL_LVDS_OUTPUT 

Info (175013): The PLL LVDS output is constrained to the region (0, 13) to (0, 15) due to related logic 

Info (175034): Assignment 1: Region must be in (0, 12) to (0, 15) due to the signal(s) routed from fractional PLL q_sys:u0|q_sys_mem_if_ddr3_emif_0_0002:mem_if_ddr3_emif_0|q_sys_mem_if_ddr3_emif_0_pll0:pll0|pll1~FRACTIONAL_PLL to the PLL LVDS output 

Info (175013): The fractional PLL is constrained to the region (0, 8) to (0, 24) due to related logic 

Info (175014): Region must be within (0, 8) to (0, 24) due to the signal(s) routed from pin clkintop_100_p to the fractional PLL 

Info (175015): The I/O pad is constrained to the location PIN_AJ28 due to: User Location Constraints (PIN_AJ28) 

Info (175034): Assignment 2: Region must be in (0, 13) to (0, 15) due to the signal(s) routed from the PLL LVDS output to PHY_CLKBUF q_sys:u0|q_sys_mem_if_ddr3_emif_0_0002:mem_if_ddr3_emif_0|q_sys_mem_if_ddr3_emif_0_p0:p0|q_sys_mem_if_ddr3_emif_0_p0_memphy:umemphy|q_sys_mem_if_ddr3_emif_0_p0_new_io_pads:uio_pads|q_sys_mem_if_ddr3_emif_0_p0_altdqdqs:dq_ddio[3].ubidir_dq_dqs|altdq_dqs2_acv_arriav_quarter_rate_mode:altdq_dqs2_inst|phy_clkbuf 

Info (175013): The PHY_CLKBUF is constrained to the region (2, 0) to (41, 0) due to related logic 

Info (175014): Region must be within (2, 0) to (41, 0) due to the signal(s) routed from the PHY_CLKBUF to Leveling Delay Chain q_sys:u0|q_sys_mem_if_ddr3_emif_0_0002:mem_if_ddr3_emif_0|q_sys_mem_if_ddr3_emif_0_p0:p0|q_sys_mem_if_ddr3_emif_0_p0_memphy:umemphy|q_sys_mem_if_ddr3_emif_0_p0_new_io_pads:uio_pads|q_sys_mem_if_ddr3_emif_0_p0_altdqdqs:dq_ddio[3].ubidir_dq_dqs|altdq_dqs2_acv_arriav_quarter_rate_mode:altdq_dqs2_inst|leveling_delay_chain_dqs 

Info (175013): The Leveling Delay Chain is constrained to the region (40, 0) to (40, 0) due to related logic 

Info (175034): Assignment 1: Region must be in (9, 0) to (86, 0) due to the signal(s) routed from DLL q_sys:u0|q_sys_mem_if_ddr3_emif_0_0002:mem_if_ddr3_emif_0|altera_mem_if_dll_arriav:dll0|dll_wys_m to the Leveling Delay Chain 

Info (175013): The DLL is constrained to the region (4, 0) to (4, 0) due to related logic 

Info (175014): Region must be within (4, 0) to (4, 0) due to the signal(s) routed from fractional PLL q_sys:u0|q_sys_mem_if_ddr3_emif_0_0002:mem_if_ddr3_emif_0|q_sys_mem_if_ddr3_emif_0_pll0ll0|pll1~FRACTIONAL_PLL to the DLL 

Info (175014): Region must be within (0, 8) to (0, 25) due to the signal(s) routed from pin clkintop_100_p to the fractional PLL 

Info (175015): The I/O pad is constrained to the location PIN_AJ28 due to: User Location Constraints (PIN_AJ28) 

Info (175034): Assignment 2: Region must be in (40, 0) to (40, 0) due to the signal(s) routed from the Leveling Delay Chain to DQS Group fed by DQS I/O pad ddr3_dqs_p[3] 

Info (175015): The I/O pad is constrained to the location PIN_AF22 due to: User Location Constraints (PIN_AF22) 

Error (175006): Could not find path between the PLL LVDS output and destination PHY_CLKBUF 

Info (175027): Destination: PHY_CLKBUF q_sys:u0|q_sys_mem_if_ddr3_emif_0_0002:mem_if_ddr3_emif_0|q_sys_mem_if_ddr3_emif_0_p00|q_sys_mem_if_ddr3_emif_0_p0_memphy:umemphy|q_sys_mem_if_ddr3_emif_0_p0_new_io_pads:uio_pads|q_sys_mem_if_ddr3_emif_0_p0_altdqdqs:dq_ddio[2].ubidir_dq_dqs|altdq_dqs2_acv_arriav_quarter_rate_mode:altdq_dqs2_inst|phy_clkbuf 

Info (175013): The PHY_CLKBUF is constrained to the region (41, 0) to (41, 0) due to related logic 

Info (175014): Region must be within (41, 0) to (41, 0) due to the signal(s) routed from the PHY_CLKBUF to Leveling Delay Chain q_sys:u0|q_sys_mem_if_ddr3_emif_0_0002:mem_if_ddr3_emif_0|q_sys_mem_if_ddr3_emif_0_p00|q_sys_mem_if_ddr3_emif_0_p0_memphy:umemphy|q_sys_mem_if_ddr3_emif_0_p0_new_io_pads:uio_pads|q_sys_mem_if_ddr3_emif_0_p0_altdqdqs:dq_ddio[2].ubidir_dq_dqs|altdq_dqs2_acv_arriav_quarter_rate_mode:altdq_dqs2_inst|leveling_delay_chain_dqs 

Info (175013): The Leveling Delay Chain is constrained to the region (72, 0) to (72, 0) due to related logic 

Info (175034): Assignment 1: Region must be in (9, 0) to (86, 0) due to the signal(s) routed from DLL q_sys:u0|q_sys_mem_if_ddr3_emif_0_0002:mem_if_ddr3_emif_0|altera_mem_if_dll_arriav:dll0|dll_wys_m to the Leveling Delay Chain 

Info (175013): The DLL is constrained to the region (4, 0) to (4, 0) due to related logic 

Info (175014): Region must be within (4, 0) to (4, 0) due to the signal(s) routed from fractional PLL q_sys:u0|q_sys_mem_if_ddr3_emif_0_0002:mem_if_ddr3_emif_0|q_sys_mem_if_ddr3_emif_0_pll0ll0|pll1~FRACTIONAL_PLL to the DLL 

Info (175014): Region must be within (0, 8) to (0, 25) due to the signal(s) routed from pin clkintop_100_p to the fractional PLL 

Info (175015): The I/O pad is constrained to the location PIN_AJ28 due to: User Location Constraints (PIN_AJ28) 

Info (175034): Assignment 2: Region must be in (72, 0) to (72, 0) due to the signal(s) routed from the Leveling Delay Chain to DQS Group fed by DQS I/O pad ddr3_dqs_p[2] 

Info (175015): The I/O pad is constrained to the location PIN_AG15 due to: User Location Constraints (PIN_AG15) 

Error (175022): The PLL LVDS output could not be placed in any location to satisfy its connectivity requirements 

Error (175022): The PHY_CLKBUF could not be placed in any location to satisfy its connectivity requirements 

Info (175029): 3 locations affected 

Info (175029): PLLLVDSOUTPUT_X0_Y13_N2 

Info (175029): PLLLVDSOUTPUT_X0_Y14_N2 

Info (175029): PLLLVDSOUTPUT_X0_Y15_N2 

Error (171000): Can't fit design in device
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2 Replies
Altera_Forum
Honored Contributor I
11 Views

Hello I have exactly the same problem. Did you find solution for this issue please? 

 

Thank you very much.
Altera_Forum
Honored Contributor I
11 Views

Hi, 

 

You can try to lock the PLL location through Assignment Editor. Find the PLL node in the RTL, and then locate in Assignment Editor and set the location.