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Clock Video Output is not working in Cyclone III FPGA

Altera_Forum
Honored Contributor II
1,176 Views

My Design consists of a clocked video output set to a resolution of 1024x768 @60Hz 65 MHz pixel clock. The data input is from the test pattern generator ip from the VIP block. 

When i build the qsys and complile my design and download the sof, it (Quartus) successfully dowloads the sof into the fpga. I had connected a HSMC-GPIO daughter board to observe the signals HS,VS,DE etc on the Oscilloscope, but none of the signals were observed in the scope. 

 

I doubt my design is correct, but am not able to troubleshoot it successfully yet, I have included my entire project file with qsys file and the top level, kindly let me know what I might have done wrong, it would be of great help. 

 

Thanks, Much appreciated for your replies. 

Sriram.
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2 Replies
Altera_Forum
Honored Contributor II
107 Views

Learn how to simulate your design.

Altera_Forum
Honored Contributor II
107 Views

Check frame size you need. I see frame size generating from TPG is 1024x768, but CVO configured as 1920x1080

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