I'm using "Clock Source" IP provided by Altera in the QSYS. I gave 250MHz in "clock frequency" parameter, but it is providing only 100MHz from its output Clock interface. I confirmed it using Signal tap logic analyzer by sampling the clock at double its frequency (based on Nyquest theorem). My question is, why Clock source IP is not able to provide the frequency I gave in Clock frequency parameter, is their something I'm missing out while generation?
FPGA : Stratix V
Part Name : 5sgxea7k2f40c2
FPGA Board : Bittware S5-PCIe-HQ
Clock pin : PIN_J23 (S5CLK16_P)
IP : Clock Source (Author : Altera Corporation, Version : 15.1)
Software : Quartus Prime Standard Edition 15.1
The Clock Source component is just for distributing a clock to the rest of the system design. It does not generate or change an incoming clock. The parameter value you mention is just for timing constraint purposes. What clock are you providing to the Platform Design system? If you want it to be 250 MHz, you have to generate it from an outside source, like a PLL.
I connected the exported input clock interface of Clock Source IP and connected it to PIN_J23 of FPGA. it might be connected to 100MHz on-board oscillator. Is it possible to generate 250MHz frequency other than using PLL?