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SBure
Beginner
412 Views

Clocked Video Input II valid resolution bit never rises

My test chain is TPG II() -> CVO II -> wire loop outside qsys -> CVI II. Video resolution is 1080, interlaced, embedded sync. I apply preset SDI 1080i in CVO and CVI parameter editor, only change it to 8 bit per color plane. I use same clock to read from CVO and write to CVI. I'm using following connections on the top level :

.alt_vip_cl_cvo_0_clocked_video_vid_clk (videoClk), // alt_vip_cl_cvo_0_clocked_video.vid_clk .alt_vip_cl_cvo_0_clocked_video_vid_data (videoData), // .vid_data .alt_vip_cl_cvo_0_clocked_video_underflow ( ), // .underflow .alt_vip_cl_cvo_0_clocked_video_vid_trs ( ), // .vid_trs .alt_vip_cl_cvo_0_clocked_video_vid_ln ( ), // .vid_ln .alt_vip_cl_cvi_0_dout_0_data ( ), // alt_vip_cl_cvi_0_dout_0.data .alt_vip_cl_cvi_0_dout_0_valid ( ), // .valid .alt_vip_cl_cvi_0_dout_0_startofpacket ( ), // .startofpacket .alt_vip_cl_cvi_0_dout_0_endofpacket ( ), // .endofpacket .alt_vip_cl_cvi_0_dout_0_ready (1'b1), // .ready .alt_vip_cl_cvi_0_clocked_video_vid_clk (videoClk), // alt_vip_cl_cvi_0_clocked_video.vid_clk .alt_vip_cl_cvi_0_clocked_video_vid_data (videoData), // .vid_data .alt_vip_cl_cvi_0_clocked_video_vid_de (1'b1), // .vid_de .alt_vip_cl_cvi_0_clocked_video_vid_datavalid (1'b1), // .vid_datavalid .alt_vip_cl_cvi_0_clocked_video_vid_locked (1'b1), // .vid_locked .alt_vip_cl_cvi_0_clocked_video_vid_f ( ), // .vid_f .alt_vip_cl_cvi_0_clocked_video_vid_v_sync ( ), // .vid_v_sync .alt_vip_cl_cvi_0_clocked_video_vid_h_sync ( ), // .vid_h_sync .alt_vip_cl_cvi_0_clocked_video_vid_color_encoding ( ), // .vid_color_encoding .alt_vip_cl_cvi_0_clocked_video_vid_bit_width ( ), // .vid_bit_width .alt_vip_cl_cvi_0_clocked_video_sof ( ), // .sof .alt_vip_cl_cvi_0_clocked_video_sof_locked ( ), // .sof_locked .alt_vip_cl_cvi_0_clocked_video_refclk_div ( ), // .refclk_div .alt_vip_cl_cvi_0_clocked_video_clipping ( ), // .clipping .alt_vip_cl_cvi_0_clocked_video_padding ( ), // .padding .alt_vip_cl_cvi_0_clocked_video_overflow ( ) // .overflow

alt_vip_cl_cvi_0_dout_0 are exported from qsys to top evel to get always ready sink for CVI.

 

The problem is bit 10(resolution bit) of CVI never asserts to 1. Bit 7(interlaced bit) and . Bit 8 (stable bit) asserted as exprected, and active, total pixels and lines counter are also correct. What can be a problem?

 

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1 Reply
Deshi_Intel
Moderator
44 Views

Hi Sergey,

 

Do you get expected output from VCO ? 

 

Do you face this issue at hardware or sim ? It will be easier to debug in sim if possible ?

 

Which Quartus version that you use ?

 

I can try look for working CVO to CVI sim design so that it's easily to compare and debug your issue. 

 

Thanks.

 

Regards,

dlim

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