FPGA Intellectual Property
PCI Express*, Networking and Connectivity, Memory Interfaces, DSP IP, and Video IP
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Configuration via Protocol - load core from QSPI

Honored Contributor II

I have a Cyclone V connected to a PCIE bus. This all works, and I have a periphery image programmed into my QSPI and I can program the core image over the PCIE bus. The advantage with this technique is that I can update the core image on the PC without having to reprogram the QSPI. The drawback with this technique is that I have to wait for the PC to boot before I can finish programming my FPGA, leaving it in a kind of limbo. Is there any way of programming the core from the same QSPI that the periphery was programmed from, but in the two stage process so that I meet the PCIE startup time requirements? 


There are some comments in the CVP user guide, on page 5-5 and 5-6 of the 15.1 CVP user guide it says: 

"The Enable autonomous PCIe HIP mode option has an effect if your design has the following twocharacteristics: 

• You are using the Flash device or Ethernet controller, instead of the PCIe link to load the core 


• You have not checked Enable Configuration via the PCIe link in the Hard IP for PCI Express 



This implies I can use a Flash device (my QSPI?) to configure the core image, but I can find no other documentation that tells me how to do this. 


Any clues greatly appreciated. 



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