Dear Altera experts,I have video component that generates the clocked video output according to the specification and every time, before the frame is started, it asserts signal "prestart_notify". This signal is than used by other components to prepare data, which are going to be merged into the clocked video stream. The signal "prestart_notify" is the only signal of Avalon conduit interface. As long as there is only one component that uses "prestart_notify" everything is OK. But now, I would like to connect another component to the same signal. But the Platform Designer (QSYS in previous versions) does not allow to connect more than one conduit end to my generation component. I have: SOURCE -------> END but I need: END2 <--------- SOURCE --------> END1 I am aware, that I could implement component in system Verilog, which will have one bit input and will produce two one bit outputs and use this component in Platform Designer or that I could export conduit outside Platform Designer as output, put as many inputs as there is Endpoint and do the connection at the top level. There are actually many ways how to deal with it, but I would like to know, if there is any way, how to simply force Platform designer to accept many endpoints for one source? The same way as there is many clock consumer connected to one clock source. Thanks for your ideas Definition of the generator and consumer is as follows: GENERATOR: add_interface prestart_notify_out conduit end set_interface_property prestart_notify_out associatedClock "" set_interface_property prestart_notify_out associatedReset "" set_interface_property prestart_notify_out ENABLED true set_interface_property prestart_notify_out EXPORT_OF "" set_interface_property prestart_notify_out PORT_NAME_MAP "" set_interface_property prestart_notify_out CMSIS_SVD_VARIABLES "" set_interface_property prestart_notify_out SVD_ADDRESS_GROUP "" add_interface_port prestart_notify_out prestart_notify_out prestart_notify Output 1 CONSUMER: add_interface reader_notify conduit end set_interface_property reader_notify associatedClock "" set_interface_property reader_notify associatedReset "" set_interface_property reader_notify ENABLED true set_interface_property reader_notify EXPORT_OF "" set_interface_property reader_notify PORT_NAME_MAP "" set_interface_property reader_notify CMSIS_SVD_VARIABLES "" set_interface_property reader_notify SVD_ADDRESS_GROUP "" add_interface_port reader_notify reader_notify prestart_notify Input 1
AFAIK this is not possible, QSys only does point to point connections for conduits. You need either to have your IP have multiple conduits out or make your own 1-to-n duplication IP.