FPGA Intellectual Property

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FPGA Intellectual Property

Discussions

I2C Controller

FIR coefficient reloading problem

strange CRA register map in PCIe ref design based on SOPC flow

Post-fit simulation of NCO MegaCore

problem about altlvds PIN assignment!

SOPC read latency question

Problem in building a LCD panel controller in SOPC

FIR Compiler troubles

Wrong address range for custom IP in SOPC

DeInterlacer, Double Buffering and Stalling Behavour

master other than NIOS cpu

Any MDIO cores complient with IEEE802.3 targeted on SIIGX

Adjusting embedded sync timing with CVO

avalon to ahb bridge

problem about reset of FFT IP

Featured Content

Tone Mapping Operator IP Malfunctioning

dynamic configuration issue of fpll from arria 10

Unable to simulate DDR3 controller

Re: ALTPLL dynamic phase shift: c0/c1 shift in opposite directions; c2 does not shift (Stratix IV)

Re: ALTPLL dynamic phase shift: c0/c1 shift in opposite directions; c2 does not shift (Stratix IV)