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Qsys Avalon-MM Master BFM Tutorial for SystemVerilog and VHDL Testbenches

Altera_Forum
Honored Contributor II
2,218 Views

Hi all, 

 

I've created a tutorial showing how to use the Avalon-MM Master BFM within SystemVerilog and VHDL testbenches. 

 

https://www.ovro.caltech.edu/~dwh/correlator/pdf/altera_avalon_bfm_master.pdf 

https://www.ovro.caltech.edu/~dwh/correlator/pdf/altera_avalon_bfm_master.zip 

 

Feedback welcome! 

 

Cheers, 

Dave 

 

PS. If any SystemVerilog Gurus read this, Appendix A has a question for you :)
4 Replies
Altera_Forum
Honored Contributor II
1,005 Views

Hi all, 

 

I've added another appendix to the document showing how Qsys VHDL abuses the use of VHDL libraries. 

 

VHDL gurus please feel free to agree or disagree with my comments :) 

 

Cheers, 

Dave
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Altera_Forum
Honored Contributor II
1,006 Views

Very Useful - thanks!

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Altera_Forum
Honored Contributor II
1,006 Views

Your tutorial is still the best starting point for using Avalon BFMs. Thanks! 

 

Since simulation performance using VHDL is questionable UVVM might be more interesting for VHDL users than the concept used by Altera/Intel. UVVM just added full Avalon MM support. UVVM stands for Universal VHDL Verification Methodology and was released as open source by the Norwegian company bitvis. You may find it on github: https://github.com/uvvm/uvvm_vvc_framework 

There is a web page also: http://www.bitvis.no/products/uvvm/ 

 

UVVM can be combined with OSVVM (http://osvvm.org/) as far as I know.
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TDhol
Beginner
1,006 Views

Hi, i am not able to open your tutorial links, are they still active?

 

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