Please provide a bit more details,
(This message was posted on behalf of Intel Corporation)
Sorry for the late reply. I forgot I asked this question and got lost in the Intel/Altera support forum transition. I'll be using Quartus Prime 18.1 Lite and a DE0-Nano dev kit.
Apologize for late response.
Please refer to the attachment for the AES3/EBU reference design.
Please note that this design was built by using an older version of software (EOL), and this design is no longer maintain or support by Intel FPGA(Altera).
Thank you Calvin!
For more complete information about compiler optimizations, see our Optimization Notice.