FPGA Intellectual Property
PCI Express*, Networking and Connectivity, Memory Interfaces, DSP IP, and Video IP
6423 Discussions

Cyclone 10 GX EMIF Package Deskew

Waseem1
Beginner
596 Views

I am designing a PCB that has a Cyclone 10 GX FPGA connected to 2 DDR3 chips in fly-by topology. I followed Intel's UG20116 EMIF IP User Guide's layout guidelines in terms of length matching address/command traces, but the document doesn't specify which signals get deskewed by Quartus and which ones don't. When it comes to package deskew, does the EMIF take care of deskewing all ADD/CMD package delays, or does it only deskew specific signals and I have to deskew specific ones on the PCB?

 

Thanks,

0 Kudos
1 Solution
AdzimZM_Intel
Employee
578 Views

Hi Waseem1,


Yes, the Quartus will take care of all address/command package delays.

You can see the description in Table 97 from the Cyclone 10 EMIF User Guide.

https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/ug-20116.pdf#page=106


Regards,

Adzim


View solution in original post

3 Replies
AdzimZM_Intel
Employee
579 Views

Hi Waseem1,


Yes, the Quartus will take care of all address/command package delays.

You can see the description in Table 97 from the Cyclone 10 EMIF User Guide.

https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/ug-20116.pdf#page=106


Regards,

Adzim


Waseem1
Beginner
563 Views

Thank you for the response. Just to be clear, does that include the control signals as well (CKE, ODT, CSn)?

0 Kudos
AdzimZM_Intel
Employee
537 Views

Hi Waseem1,


That signals should be included in Command pins.

You can refer to Table 113 in EMIF Cyclone 10 User Guide for the pin options.

https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/ug-20116.pdf#page=116


Thanks,

Adzim



0 Kudos
Reply