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Cyclone V EPCQ-A remote update

I have a project with remote update option for 5CEBA2F17 and EPCQ32A. I have an application image developed earlier and working well.

I made a factory image having a remote update (ALT_REMOTE) core with a state machine, setting the AnF bit, disabling the watchdog timer, setting start address and reconfiguring to the app image. It worked well. I made the combined pof with "Convert Programming Files" option starting the factory image at 0x0 and app image at 0x100000.

A Cypress USB FIFO interface was added to the design to download the new image into FPGA through an internal dcfifo (to move from 48MHz to 10MHz). For EPCQ programming an ASMI (ALTASMI_PARALLEL) core was instantiated and connected to dcfifo.

After this modification of the design, it never loads the app image even if update is not needed. I was searching in the datasheets if these cores need for any cooperation between them or can drive the EPCQ pins independently but could not find anything. I checked the Cyclone V reconfig ref design but the corresponding part was completely missing from the package so it did not help.

Does anyone know how these two IP cores are connected together physically within the chip? Do they need some special connection defined somehow? Maybe I should add the POF checking option to remote update core and connect to ASMI directly? But in this case I would have to share the ASMI between remote update core and my own download design somehow.

Any experience or advise for this project?

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Hi,

 

Thank you for contacting Intel community.

For Cyclone V remote update, have you refer to Remote Update Intel® FPGA IP User Guide below:

https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/ug_altremote.pdf

 

You can also refer to Intel community knowledge base below:

https://community.intel.com/t5/FPGA-Wiki/Remote-update-for-Cyclone-V/ta-p/735947

 

Let me know your feedback.

 

Thanks.

 

Regards,

Aiman

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Hi Aiman,

Thank you for your response and links.

Unfortunately I have no Qsys in my design. Does this core has a detailed documentation?

I already made a design containing a factory image and an application image. Factory image contained the referred altremote core (Remote Update hard IP) and I was able to load the app image by the factory image automatically at startup (by a simple state machine).

Now I am stocked how to write a new application image into my EPCQ32A. I tried to add an ASMI core (altasmi) and load it from an external FIFO source by a small Verilog code but now the altremote core does not work even if I disable the flash writing and I do not understand why. Perhaps the ASMI core switches off the connection of the altremote to the flash but I am not sure and do not know how to test it.

I tried the design referred in ug_altremote.pdf page 40. It seems to be very similar to mine (based on AN603) but the code what I wanted to check is completely missing from the Application image. Is this a valid design?

Istvan

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Hi,


If you are using ASMI 1, there is an issue to single byte write, kindly refer below for further info and workaround:

https://www.intel.com/content/altera-www/global/en_us/index/support/support-resources/knowledge-base...


Below if the workaround if you are using ASMI II:

https://www.intel.com/content/altera-www/global/en_us/index/support/support-resources/knowledge-base...


Thanks.


Regards,

Aiman


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