Stratix 10 E-TILE reset sequence

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Stratix 10 E-TILE reset sequence

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Hello,

I have troubles with E-TILE transceiver reset sequence after device configuration.

I'm using the transceiver in Native PHY mode with reset controller (Local TRS). The transceiver serial signals are connected to QSFP loopback module on PCB.

I'm preforming digital and analog reset as described in Chapter 6.2.1 of E-Tile Transceiver PHY User Guide. I can observe that after deasserting digital reset tx_pma_ready and rx_pma_ready signals do assert. However rx_ready signal is never asserted.

If I enable TX PRBS generator and internal loopback in the transceiver then rx_ready signal is asserted.

What could cause such behavior?

Thank you!

Best regards,

Mikhail

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