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Altera_Forum
Honored Contributor I
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Cyclone V GT, Custom PHY IP Core

Hi, 

I am using a Cyclone V GT FPGA and and HSMC SFP card trying to implement a loopback test, through fiber optics. Since now, it is successfully implemented according to a tutorial I found based on a Qsys system. The system uses the Custom PHY IP Core, and a data pattern generator/checker without 8b/10b encoding/decoding. I have tried to remove the pattern generator and checker and disable the Avalon interface of Custom PHY, because I want to send my own frame through Tx side and observe it from Rx side. Additionally, 8b/10b encoding has to be used, but I cant figure out the customization of options(parameters) about that and the setup of alignment. Should there be a part, where I am supposed to describe my sent data format(like: data, data, control), for alignment sake? Is there any way to do that, cause right now by exporting the parallel data input and output and by using SignalTap, I can only observe a non-deterministic shifting(or drifting) of output data compared to input data, which is probably synchronization issue. 

 

Thanks 

Bill 

:confused::confused::confused:
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