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Cyclone V and simulation of ASMI Parallel

Altera_Forum
Honored Contributor II
1,173 Views

Hello everyone, 

 

I am trying to simulate ASMI Parallel IP with no obvious success. I really need this block to get access to the external FLASH device. To get familiar with this IP, I decided to use its simplest (IMO) function: "bulk_erase". It would be very easy to validate in hardware and should be simple to implement and simulate. So, I went though the process of creating ASMI Parallel using QSYS and then added the .qsys file to my test project. It compiles fine, but for some reason the Model-Sim gives me all these errors: 

# Loading EPCQ_CONTROLLER.EPCQ_CONTROLLER_asmi_parallel_0# ** Error (suppressible): (vsim-10000) e:/otherprojects/devfpga/asmi_test/phy/db/ip/epcq_controller/submodules/epcq_controller_asmi_parallel_0.v(321): Unresolved defparam reference to 'addbyte_cntr' in addbyte_cntr.width.# Time: 0 ps Iteration: 0 Instance: /tb_ru/UUT/epcq/asmi_parallel_0 File: e:/otherprojects/devfpga/asmi_test/phy/db/ip/epcq_controller/submodules/epcq_controller_asmi_parallel_0.v# ** Error (suppressible): (vsim-10000) e:/otherprojects/devfpga/asmi_test/phy/db/ip/epcq_controller/submodules/epcq_controller_asmi_parallel_0.v(322): Unresolved defparam reference to 'addbyte_cntr' in addbyte_cntr.lpm_type.# Time: 0 ps Iteration: 0 Instance: /tb_ru/UUT/epcq/asmi_parallel_0 File: e:/otherprojects/devfpga/asmi_test/phy/db/ip/epcq_controller/submodules/epcq_controller_asmi_parallel_0.v# ** Error (suppressible): (vsim-10000) e:/otherprojects/devfpga/asmi_test/phy/db/ip/epcq_controller/submodules/epcq_controller_asmi_parallel_0.v(342): Unresolved defparam reference to 'gen_cntr' in gen_cntr.width.# Time: 0 ps Iteration: 0 Instance: /tb_ru/UUT/epcq/asmi_parallel_0 File: e:/otherprojects/devfpga/asmi_test/phy/db/ip/epcq_controller/submodules/epcq_controller_asmi_parallel_0.v# ** Error (suppressible): (vsim-10000) e:/otherprojects/devfpga/asmi_test/phy/db/ip/epcq_controller/submodules/epcq_controller_asmi_parallel_0.v(343): Unresolved defparam reference to 'gen_cntr' in gen_cntr.lpm_type.# Time: 0 ps Iteration: 0 Instance: /tb_ru/UUT/epcq/asmi_parallel_0 File: e:/otherprojects/devfpga/asmi_test/phy/db/ip/epcq_controller/submodules/epcq_controller_asmi_parallel_0.v# ** Error (suppressible): (vsim-10000) e:/otherprojects/devfpga/asmi_test/phy/db/ip/epcq_controller/submodules/epcq_controller_asmi_parallel_0.v(363): Unresolved defparam reference to 'stage_cntr' in stage_cntr.width.# Time: 0 ps Iteration: 0 Instance: /tb_ru/UUT/epcq/asmi_parallel_0 File: e:/otherprojects/devfpga/asmi_test/phy/db/ip/epcq_controller/submodules/epcq_controller_asmi_parallel_0.v# ** Error (suppressible): (vsim-10000) e:/otherprojects/devfpga/asmi_test/phy/db/ip/epcq_controller/submodules/epcq_controller_asmi_parallel_0.v(364): Unresolved defparam reference to 'stage_cntr' in stage_cntr.lpm_type.# Time: 0 ps Iteration: 0 Instance: /tb_ru/UUT/epcq/asmi_parallel_0 File: e:/otherprojects/devfpga/asmi_test/phy/db/ip/epcq_controller/submodules/epcq_controller_asmi_parallel_0.v# ** Error (suppressible): (vsim-10000) e:/otherprojects/devfpga/asmi_test/phy/db/ip/epcq_controller/submodules/epcq_controller_asmi_parallel_0.v(384): Unresolved defparam reference to 'wrstage_cntr' in wrstage_cntr.width.# Time: 0 ps Iteration: 0 Instance: /tb_ru/UUT/epcq/asmi_parallel_0 File: e:/otherprojects/devfpga/asmi_test/phy/db/ip/epcq_controller/submodules/epcq_controller_asmi_parallel_0.v# ** Error (suppressible): (vsim-10000) e:/otherprojects/devfpga/asmi_test/phy/db/ip/epcq_controller/submodules/epcq_controller_asmi_parallel_0.v(385): Unresolved defparam reference to 'wrstage_cntr' in wrstage_cntr.lpm_type.# Time: 0 ps Iteration: 0 Instance: /tb_ru/UUT/epcq/asmi_parallel_0 File: e:/otherprojects/devfpga/asmi_test/phy/db/ip/epcq_controller/submodules/epcq_controller_asmi_parallel_0.v# ** Error (suppressible): (vsim-10000) e:/otherprojects/devfpga/asmi_test/phy/db/ip/epcq_controller/submodules/epcq_controller_asmi_parallel_0.v(416): Unresolved defparam reference to 'sd4' in sd4.enable_sim.# Time: 0 ps Iteration: 0 Instance: /tb_ru/UUT/epcq/asmi_parallel_0 File: e:/otherprojects/devfpga/asmi_test/phy/db/ip/epcq_controller/submodules/epcq_controller_asmi_parallel_0.v# ** Error (suppressible): (vsim-10000) e:/otherprojects/devfpga/asmi_test/phy/db/ip/epcq_controller/submodules/epcq_controller_asmi_parallel_0.v(417): Unresolved defparam reference to 'sd4' in sd4.lpm_type.# Time: 0 ps Iteration: 0 Instance: /tb_ru/UUT/epcq/asmi_parallel_0 File: e:/otherprojects/devfpga/asmi_test/phy/db/ip/epcq_controller/submodules/epcq_controller_asmi_parallel_0.v# Error loading design 

 

I know people has done this before, but I was not able to find any examples on-line on how to do that. The attached is a test project with a state machine and a test bench. I would really appreciate if someone would help me to figure this out and get going with the project. 

 

Thanks, 

Yev
0 Kudos
2 Replies
Altera_Forum
Honored Contributor II
117 Views

Hi ymakisme, 

 

I face a similar problem when I try to simulate a code where I just read the memory capacity ID of the EPCQ128 using Altera ASMI parallel IP core.  

I get 1 error:  

Unresolved defparam reference to 'sd4' in sd4.enable_sim. 

 

Did you solve your problem? If yes, please specify what changes you made. It'll be really helpful for me. 

 

Thankyou.
Altera_Forum
Honored Contributor II
117 Views

Hi , 

I raised a SR in Altera and this problem is because of version compatability. Make sure the simulation tool you use has the libraries of the Quartus version that you used to generate the IP.
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