when i use CycloneV native transceiver IP core, the function simulation is OK.But when i put the IP into my project and compiling the project,there will be some errors. The release of quartus is 13.1,the error message list blow,please help me to see how i fix these?
Error: HSSI PMA TX Buffer node 'xcvr_native_phy_ip cvr_native_phy_ip_inst|altera_xcvr_native_sv
cvr_native_phy_ip_inst|sv_xcvr_native
en_native_inst.xcvr_native_insts[0].gen_bonded_group_native.xcvr_native_inst|sv_pma:inst_sv_pma|sv_tx_pma:tx_pma.sv_tx_pma_inst|sv_tx_pma_ch:tx_pma_insts[0].sv_tx_pma_ch_inst|tx_pma_ch.tx_pma_buf.tx_pma_buf' is not properly connected on the 'DATAOUT' port. It must be connected to one of the valid ports listed below.
Info: Can be connected to I port of stratixv_io_obuf WYSIWYG
Error: Input port REFIQCLK0 of xcvr_native_phy_ip cvr_native_phy_ip_inst|altera_xcvr_native_sv
cvr_native_phy_ip_inst|sv_xcvr_native
en_native_inst.xcvr_native_insts[0].gen_bonded_group_native.xcvr_native_inst|sv_pma:inst_sv_pma|sv_rx_pma:rx_pma.sv_rx_pma_inst|rx_pmas[0].rx_pma.cdr_refclk_mux0 atom must be connected when parameter cdr_refclk_select is set to 'ref_iqclk0''
