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We have connected four lane PCIe interface (with lane reversal) between cyclone 10 GX part number 10CX105YF780I6G and a PCIe switch. The PCIe link is not up. Let us know if cyclone 10 device supports lane reversal also how to know which PCIe lanes can be used for x4 configuration ( apart from simulation ) ?.Does the transceiver document mentions which lanes can be used for x4 interface? Which document i should check to validate this ? the lanes used on fpga are
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To check if the transceiver section power and clock is fine , are there any registers inside cyclone 10 to verify these ?
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