DDR2 High Performance Controller settings

[Altera_Forum]

I am having a problem with Altera's DDR2 High Performance Controller v7.2 to control a single DIMM. 

 I am using the controller in half-rate Native interface mode. The DIMM has 2 chip selects, 11 Column Address bits, 14 Row Address bits, and 3 Bank bits. Bit 10 is the precharge bit. DQ width is 72 bits. The MegaWizard plug-in manager correctly reflects these values, and the amount of memory predicted is correct.  When setting local_address[26:0] == 0x01, the memory controller addresses Row 0, Column 0x8 (mem_addr[3] == 1). When setting local_address[26:0] == 0x80, the memory controller addresses Row 0, Column 0x400 ({mem_addr[11],mem_addr[9:0]} = 11'h400). I never see mem_addr[2] change during the column phase.  Writing to local_address 0x100 does not switch to the next row. {mem_addr[11],mem_addr[9:0]} = 0x0. mem_addr[12] (which is not a valid column bit) does not go high either. The overall effect of this is I get a stuck address bit error when addressing local_address 0x100.  I cannot simply shift the entire address bus over one bit because the row address bits are correct and start at A0, and the precharge address bit is in the correct position.  Any thoughts?

[Altera_Forum]

Also, artificially lowering the number of column bits does not make the problem go away - it just makes the error happen at a lower address.

[Altera_Forum]

This totally sounds like what I mentioned here: 

http://alteraforum.com/forum/showpost.php?p=21095&postcount=9

[Altera_Forum]

--- Quote Start ---  This totally sounds like what I mentioned here: http://alteraforum.com/forum/showpost.php?p=21095&postcount=9  --- Quote End ---    Right - it's as if the controller thinks that the memory is twice as wide as it actually is - but the settings look correct.  It's a half rate controller. The DDR bus is 64 bits + ECC (8 bytes)  The local bus is 256 bits (32 bytes).  Thus, every incrementation of local_address by 1 ( 1*32 = 32) should increment the DDR address by 4 ( 4 * 8 = 32)  Instead, the DDR address is being incremented by 8 - and then it's running out of column addresses.  Also, about your post:   --- Quote Start ---  ... the address locations you can access are only multiples of the data width.   For example, a 64-bit data width, addressing can only happen at these addresses : 0x0, 0x64, 0x128, 0x192, 0x256...etc   --- Quote End ---   You can only address locations that are multiples of the data width IN BYTES, so a 64 bit address bus can only address every 0x8 bytes, not every 0x64, because the addresses are byte aligned, not bit aligned. Also, the hex nomenclature 0x64 would actually be every 100 addresses decimal. Every 64 decimal bytes would actually be addresses every 0x40 hexidecimal bytes.

[Altera_Forum]

you're right wcalkins, it is in bytes.  

i'm getting a bit rusty.