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PCI Express*, Networking and Connectivity, Memory Interfaces, DSP IP, and Video IP

DDR2 controller help

Altera_Forum
Honored Contributor II
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Hi, 

 

I am following the example "Using the SDRAM on Altera’s DE2 Board with Verilog Designs" using Qsys.  

 

I have built the system and loaded it on the FPGA but I don't see any example on how to test that the RAM controller is working. It only shows how to test the switches and LEDs. 

 

How can I write data to a specific RAM address and read it back to see if it is correct? How exactly does it work? If anyone knows more , It would be very helpful. 

 

Thanks, 

Paul
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