- Mark as New
- Bookmark
- Subscribe
- Mute
- Subscribe to RSS Feed
- Permalink
- Email to a Friend
- Report Inappropriate Content

Hello everybody,

I try to FIR Compiler simulation. I want to know how to calculate Gain from simulation result. I think that " Gain = 10 log (Vin / Vout)^2 ", but Fir Compiler's input data bit and output data bit is different. My setting is following. 1. LPF 2. cut off frequency : 1.25MHz 3. input 8bit 4. output 8bit (Full bit is 22bit, and LSB 14bit Truncate) I made input 3MHz input data, and input data is 100 ~ -100. I simulation it, but output data is 49 ~ -50. I want to 0db Gain result, but result is -6db. This method is different? If truncate the bit, it effect on the calculation of the gain? Could you tell me please? I will attach the project.(ver 13.1) https://www.alteraforum.com/forum/attachment.php?attachmentid=9261 Thanks for read.Link Copied

11 Replies

- Mark as New
- Bookmark
- Subscribe
- Mute
- Subscribe to RSS Feed
- Permalink
- Email to a Friend
- Report Inappropriate Content

The worst-case gain depends on whether you want programmable coefficients or not.

For example, if you have 100 8-bit taps, then the worst-case gain is the sum of 100 0xFF values, i.e., a bit-growth of log2(100). If your coefficients are fixed, then the worst-case bit-growth occurs for the worst-case signal made from sign(h[n]), where h[n] are your coefficients. This signal makes the FIR filter output peak sum(abs(h[n])). --- Quote Start --- I want to 0db Gain result, but result is -6db --- Quote End --- FIR filters are generally designed to maximize the dynamic range, and then the "gain" is whatever, and you just deal with it, eg., by scaling the output to the nearest power of 2, or using a multiplier to apply gain, and then re-quantizing the result (via saturation and rounding). Depending on what you are filtering, you do not always know ahead-of-time what the output power in the band will be, so the filter output gain may need to be programmable. Cheers, Dave- Mark as New
- Bookmark
- Subscribe
- Mute
- Subscribe to RSS Feed
- Permalink
- Email to a Friend
- Report Inappropriate Content

Hi Dave,

Thank you for reply, I understood "I should reduce taps, and reduce bit-growth", "I should edit coefficients, and reduce sun(abs(h[n]))", and so on. Excuse me, may I addition question? If I designed to maximize the dynamic range, how to calucurate gain? I think that input.txt and output.txt is voltage. example input bits : 8bit input data : 100 ~ -100 bit-growth : 6.6 (log2(100)) output bits : 15bit output data at one point : 25500 (sum of 100 0xFF values) The following calculations correct? Gain = 10 log (Vin / Vout)^2 = 10 log (100 / 25500)^2 = 48dB It seems to be amplified. or I should convert out put max range into input data range (100 ~ -100) by user logic? Thanks, jas39- Mark as New
- Bookmark
- Subscribe
- Mute
- Subscribe to RSS Feed
- Permalink
- Email to a Friend
- Report Inappropriate Content

- Mark as New
- Bookmark
- Subscribe
- Mute
- Subscribe to RSS Feed
- Permalink
- Email to a Friend
- Report Inappropriate Content

Hi Dave,

Thank you very much for reply. Sorry, I don't have requirements because I use FIR Filter for understanding how to use FIR compiler IP. How about following requestments? 1. LPF 2. cut off frequency : 1.25MHz 3. input 8bit 4. ADC sampling frequency : 3MHz ( http://www.ti.com/lit/ds/symlink/adc1173.pdf Does it need enough bigger than cut off frequency?) 5. Pass-band ripple requirement : 0.3dB 6. Stop-band rejection requirement : 40dB Thanks, jas39- Mark as New
- Bookmark
- Subscribe
- Mute
- Subscribe to RSS Feed
- Permalink
- Email to a Friend
- Report Inappropriate Content

Hi Dave,

Thank you very much for reply. Sorry, I don't have requirements because I use FIR Filter for understanding how to use FIR compiler IP. How about following requestments? 1. LPF 2. cut off frequency : 1.25MHz 3. input 8bit 4. ADC sampling frequency : 3MHz ( http://www.ti.com/lit/ds/symlink/adc1173.pdf Does it need enough bigger than cut off frequency?) 5. Pass-band ripple requirement : 0.3dB 6. Stop-band rejection requirement : 40dB Thanks, jas39- Mark as New
- Bookmark
- Subscribe
- Mute
- Subscribe to RSS Feed
- Permalink
- Email to a Friend
- Report Inappropriate Content

Hi Dave,

Thank you very much for reply. Sorry, I don't have requirements because I use FIR Filter for understanding how to use FIR compiler IP. How about following requestments? 1. LPF 2. cut off frequency : 1.25MHz 3. input 8bit 4. ADC sampling frequency : 3MHz ( ttp://www.ti.com/lit/ds/symlink/adc1173.pdf Does it need enough bigger than cut off frequency?) 5. Pass-band ripple requirement : 0.3dB 6. Stop-band rejection requirement : 40dB Thanks, jas39- Mark as New
- Bookmark
- Subscribe
- Mute
- Subscribe to RSS Feed
- Permalink
- Email to a Friend
- Report Inappropriate Content

- Mark as New
- Bookmark
- Subscribe
- Mute
- Subscribe to RSS Feed
- Permalink
- Email to a Friend
- Report Inappropriate Content

Regarding 0dB gain (unity) it is defined for a given reference frequency point e.g. dc for LPF.

It also affects signal mean power and final power depends how much power you chop off. for dc unity gain set sum of coeffs to 1 (or sum of every single polyphase to 1 if upsampling)- Mark as New
- Bookmark
- Subscribe
- Mute
- Subscribe to RSS Feed
- Permalink
- Email to a Friend
- Report Inappropriate Content

Hi Dave and kaz,

Thank you very much for reply. I don't understand the digital filter enough, so I'll think it over, and I will understand.- Mark as New
- Bookmark
- Subscribe
- Mute
- Subscribe to RSS Feed
- Permalink
- Email to a Friend
- Report Inappropriate Content

- Mark as New
- Bookmark
- Subscribe
- Mute
- Subscribe to RSS Feed
- Permalink
- Email to a Friend
- Report Inappropriate Content

If you've never designed analog filters before, take a read of this document:

http://www.ovro.caltech.edu/~dwh/carma_board/ad9956_tests.pdf Look on pages 18 to 26, where I document how I designed a 50MHz low-pass filter. On p25 note how the stop-band rejection of the filter is better than 60dB a little above 50MHz. This signal could be sampled using an ADC clock at around 120MHz, and the aliased energy would be less than the quantization noise floor of the ADC, i.e., the aliased energy would make no difference to the sampled signal. Your 1.25MHz signal would need to be analog filtered in a similar way before sampling it with an ADC. Cheers, DaveTopic Options

- Subscribe to RSS Feed
- Mark Topic as New
- Mark Topic as Read
- Float this Topic for Current User
- Bookmark
- Subscribe
- Printer Friendly Page