DDR2 controller: mess with different Q. versions

[Altera_Forum]

Hi, 

 since this is my first post here hello to all. I've spent the last 18 months working with Xilinx stuff and my company switches to Altera for this years solution so naturally there are some problems for me to overcome right now.  A large part of the design I have was done externally and I guess they started with Quartus version 7.2, then (maybe with command-line driven synthesis) continued with the 8.1 version. I had problems with the 7.2 version on my PC and installed 8.1 but I still have problems.  At the moment I can't solve this problem  "Error: Can't find port "ocp_enable" in OpenCore Plus entity "auk_ddr2_hp_init". -- OpenCore Plus specification file is invalid"  that occurrs during synthesis. There is already a thread in this forum about problems with different entity declarations in an opencore plus entity and the solution is to delete the files and let the SOPC_Builder (or the MegaWizard?) regenerate it, but I simply can't locate the source for the file auk_ddr2_hp_init.ocp. Can anyone point me to the right place or give a hint how to find out where this file came from?  Thanks and regards flint

[Altera_Forum]

Hmm, I now "solved" the problem by deleting the files and copying two ocp files to the same directory. Quartus seems to be ok with it but I am quite unsure this will work out correctly.

[Altera_Forum]

hi, 

im using stratix development board and im having a same problem. i dont know what your mean is to resolve this problem. please instruct me clearly . thanks

[Altera_Forum]

It's been quite some time so I can't remember exactly. I guess it is a problem with the OpenCore Plus license and the ocp_enable port is just a dummy port to check for validity of the license. But I am not completely sure about that.

[Altera_Forum]

thank for your respond , 

when i used quartus 8.0, compile hadn't error, but im using quartus 8.1 and compile has that error. i wonder how there are diference between two that vesions