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DDR2 synthesis error with Arria II Gx

Honored Contributor II

Hi Folks, 

I get the following error message when I try to compile my design using DDR2 controller. 


Error (17044): Illegal connection found on I/O input buffer primitive ddr2_sodimm:inst2|ddr2_sodimm_controller_phy:ddr2_sodimm_controller_phy_inst|ddr2_sodimm_phy:ddr2_sodimm_phy_inst|ddr2_sodimm_phy_alt_mem_phy:ddr2_sodimm_phy_alt_mem_phy_inst|ddr2_sodimm_phy_alt_mem_phy_dp_io:dpio|dqs_group[0].ddr2_with_dqsn_buf_gen.dqs_inpt_ibuf. Source IO ddr2_sodimm:inst2|ddr2_sodimm_controller_phy:ddr2_sodimm_controller_phy_inst|ddr2_sodimm_phy:ddr2_sodimm_phy_inst|ddr2_sodimm_phy_alt_mem_phy:ddr2_sodimm_phy_alt_mem_phy_inst|ddr2_sodimm_phy_alt_mem_phy_dp_io:dpio|dqs_group[0].ddr2_with_dqsn_buf_gen.dqs_obuf also drives out to other destination than the buffer. 


I have checked the previous posts related to this error and accordingly changed the design in 2 ways: 

1.Adding the port vector i.e [0:0] for the corresponding single bit signals such as mem_cas_n, mem_cke, mem_cs_n,mem_dm,mem_odt,mem_ras_n,mem_we_n etc). 

2.Changing the clocks as bidirectional in that module.(inout instead of output). 


Request to please advice on the same. 

Any suggestion would be of great help. 

Thanks in advance!! 

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Honored Contributor II

This is an old thread, but for the benefit of others, I was seeing this compile error when I was prototyping with my DDR2 signals defined, but not actually connected yet to the ALTMEMPHY IP.

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