DDR3: Can 1 controller control two memory chips

[Altera_Forum]

All, 

 We currently use altmemphy with our own custom controller. We have succesfully used it many times but we want to now increase our memory interface width to increase bandwidth.   We currently use one x16 DDR3 part driven by a half rate controller. If I wanted to use two x16 parts, could I drive it with 1 controller (i.e. 1 PLL) still with dedicated routing for each chip?. Due to the layout and the clock speed (400MHz in ARRIA2 GX) I want to use dedicated address lines etc.. for each chip. I have seen other posts which talk about this but they get errors when they try to split the address lines outside the IP due to altmemphy using primitives.   I have attached a picture of what I mean. Is option 3 possible?   Option1: I believe you can do this as this is how DIMMs are wired up but it doesn't give me the dedicated address lines   Option2: Is possible but uses two PLLs.   Option3: Is what I would like to do but I worry about getting the multiple address lines and that my timing margin will reduce if the controller has to try to adjust the timing for now 32 bits instead of 16. It uses 1 PLL and 1 DLL   Any input would be gratefully received :).   Thanks   C

[Altera_Forum]

Address command lines run at half the speed (2T) of the DQ lines. So speed issues shouldn't be important here.  

 Option 1 requires leveling which is not support in Arria II.  Use balance tree topology on the PCB (split the addr/cmd signals on the PCB), you need to perform trace simulations first. (which at this speed you should do for any layout)

[Altera_Forum]

std_logic, 

 Thanks for taking the time to reply. That gives me a good push in the right direction.   Thanks   C