I'm using Arria V GT Dev kit. I want to interface with DDR3 for MPFE. I'm using DDR3 SDRAM with Uniphy IP. Dev board has 2 FPGA's. FPGA-1 is connected to DDR3A (U28,U21,U18,U11,U7) as soft IP controller and FPGA-2 is connected to DDR3B(U12,U6) as Hard IP controller. If i instantiate the Hard IP in FPGA-1 does it creates any problem. We want to use Hard IP , since it supports Multiport Front End (MPFE) which is not available in soft IP. regards Vinod Kumar.