DDR3- Multi-port Front End

FPGA Intellectual Property

PCI Express*, Networking and Connectivity, Memory Interfaces, DSP IP, and Video IP

DDR3- Multi-port Front End

990 Views

Hello,

I'm using Arria V GT Dev kit. I want to interface with DDR3 for MPFE. I'm using DDR3 SDRAM with Uniphy IP.

Dev board has 2 FPGA's. FPGA-1 is connected to DDR3A (U28,U21,U18,U11,U7) as soft IP controller and FPGA-2 is connected to DDR3B(U12,U6) as Hard IP controller.

If i instantiate the Hard IP in FPGA-1 does it creates any problem. We want to use Hard IP , since it supports Multiport Front End (MPFE) which is not available in soft IP.

regards

Vinod Kumar.

Link Copied

0 Replies

Community support is provided during standard business hours (Monday to Friday 7AM - 5PM PST). Other contact methods are available here.

Intel does not verify all solutions, including but not limited to any file transfers that may appear in this community. Accordingly, Intel disclaims all express and implied warranties, including without limitation, the implied warranties of merchantability, fitness for a particular purpose, and non-infringement, as well as any warranty arising from course of performance, course of dealing, or usage in trade.

For more complete information about compiler optimizations, see our Optimization Notice.