DDR3 SDRAM Controller with UniPHY - Generate HDL Error in QSYS

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DDR3 SDRAM Controller with UniPHY - Generate HDL Error in QSYS

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Hi,

I am new to design with Altera and trying to examine it's tools. For this purpose I have been searched for reference designs and tried to follow the reference design given in the following link.

( http://www.alterawiki.com/wiki/design_example_-_stratix_iv_ddr3_sdram_uniphy_400mhz_x8 )

However, when I try to generate HDL files in QSYS it gives multiple errors. Most of these errors are like as below:

error: p0: error during execution of script generate_altdqdqs.tcl: add_parameter: string not allowed for eparametertype, must be in {[integer, natural, positive, boolean, std_logic, std_logic_vector, string, string_list, integer_list, long, float]}

What can be the reason of this?

Best Regards,

mdursun

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