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Altera_Forum
Honored Contributor I
999 Views

DDR3 SDRAM Unimemphy issue with qsys design

Hi there, 

 

I am beginner with DDR3 and try to integrate DDR3 SDRAM(MT41J128M16) with NIOS.My qsys design is having NIOS,DDR3 SDRAM Controller,JTAG UART and interconnect bridges. 

The issue is that when i generate the qsys design its get generated successfully but having warning with  

"Warning: System.ddr3_bot: 'Quick' simulation modes are NOT timing accurate. Some simulation memory models may issue warnings or errors." 

should i ignore this warning or is there any parameter that i have missed to configure properly. 

 

 

 

waiting for your reply. :( 

 

regards, 

Hitesh Zanzmera
0 Kudos
3 Replies
Altera_Forum
Honored Contributor I
37 Views

Moving out of the SoC section so that you'll have people who know this answer see the post. 

 

To be honest I'm not sure what that message means but I have ignored it many times and never had an issue. I suspect what it's trying to say is that the model being generated for the memory controller is functional only and so if you connect it to the timing memory model then bad things could happen.  

 

Make sure you go through this document if you have not already done so if you plan on simulating code running on Nios II: http://www.altera.com/literature/an/an351.pdf
Altera_Forum
Honored Contributor I
37 Views

Thanks BadOmen.

Altera_Forum
Honored Contributor I
37 Views

By the way I just noticed a setting in the Uniphy controller I have never noticed before called "Enable support for the Nios II ModelSim flow in Eclipse" in the UI. I recommend enabling that option since I suspect the code memory intialization will not work correctly without it.

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