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Altera_Forum
Honored Contributor I
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DDR3 SDRAM Unimemphy issue with qsys design

Hi there, 

 

I am beginner with DDR3 and try to integrate DDR3 SDRAM(MT41J128M16) with NIOS.My qsys design is having NIOS,DDR3 SDRAM Controller,JTAG UART and interconnect bridges. 

The issue is that when i generate the qsys design its get generated successfully but having warning with  

"Warning: System.ddr3_bot: 'Quick' simulation modes are NOT timing accurate. Some simulation memory models may issue warnings or errors." 

should i ignore this warning or is there any parameter that i have missed to configure properly. 

 

 

 

waiting for your reply. :( 

 

regards, 

Hitesh Zanzmera
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