DDR4 controller arria 10 calibration issues.

[senjd]

In my arria 10 project, i am using ddr4 controller of intel ip with speed bins 1600 cl 12. After loading the bit file in to fpga, local_cal_success hits high. Which says that calibration passes. But while trying to writing or reading, calibration hits low at random address. I had generated the example design with same with emif debug toolkit. It shows the same. First time it passes up the calibration. While re run the calibration, it fails. Does anyone having the same issue?

[AdzimZM_Intel]

Hi senjd,

May I know the EMIF IP setting that you used?

What is the Quartus version that has been used to generate the IP?

Why are you doing calibration again?

I'm not clear about this.

Maybe you can provide a little more explanation for better understanding.

Thanks & Regards,

Adzim

[senjd]

Hi AdzimZM_Intel,

Thanks for the reply.

I am using preset from DDR4-1600L CL 12 COMPONENT 1CS 8 Gb (512Mb x16)

Quartus version is 22.2

I had state machine to write/read the data into the ddr4 controller avalon interface. Enabling of the state machine triggers from jtag through tcl in system console.

When i tried to write the data or read the data from ddr4 then each time at random address, local_cal_pass deasserts, which means calibrarion has been failed somehow.

So i tried regenrated example design of emif controller and using emif debug toolkit to confirm re run calibration multiple time to check the status of calibration.

So, what causes the calibration status failing at random address of write or read. ?

Thanks

[AdzimZM_Intel]

Hi senjd,

How about the local_cal_fail signal?

Is it low or high?

The issue may be due to the OCT recalibration because the Periodic OCT has been enabled in the IP.

You may disable the option because the Periodic OCT is only required for high memory frequency (1200MHz and above).

Regards,

Adzim

[senjd]

Hi AdzimZM_Intel,

While doing the transactions, local_cal_success goes to low at random address. But local_cal_fail remails low.

About oct re calibration

Ddr4 controller ip system messages says :

Periodic OCT re calibration is disabled because the interface uses calibrated IO standard for either address, command and clock signals

The interface will have reduced read capture timing margin due to periodic OCT re calibration being disabled.

It seems like its already disabled.
I am using micron ddr4 MT40A512M16TB-062E:J. Which is having maximum speed bins till 3200MBps. But i am using 1600 speed bins as my fpga device does not support this speed grade.
So, is there anything i am missing?

[AdzimZM_Intel]

Hi senjd,

I can check the EMIF IP setting in your design but I need the design or the EMIF IP file.

Are you able to share the design file?

If you cannot make it, then you can snapshot the IP configuration from the IP Parameter Editor GUI and post here.

Are you using your own custom board or Intel development kit?

You may provide the device OPN as well.

Regards,

Adzim

[AdzimZM_Intel]

Hi senjd,

May I know any update on this thread?

Regards,

Adzim

[senjd]

Hi AdzimZM_Intel,

Yes. It is SOC Design. 
there is an update over it. It was due to reference clock of the ddr controller. clock was some how not proper with differential signals.

Thanks for your replies. 

Thanks,

senjd

[AdzimZM_Intel]

Hi senjd,

Thanks for the update.

Great that you are able to find the root cause. Is there anything I can help you in this issue?

Regards,

Adzim

[senjd]

Not as of now. thanks a lot for helping out. appreciate it. 

[AdzimZM_Intel]

I’m glad that your question has been addressed, I now transition this thread to community support. If you have a new question, feel free to open a new thread to get the support from Intel experts. Otherwise, the community users will continue to help you on this thread. Thank you.