DE2 board Codec help

Altera_Forum · ‎06-12-2012

Hello everyone,

I am trying to interface the wolfson codec in the de2 board. i've written a code to send data the control registers of the codec. since i want to use the microphone i sent data to register4 (boost its volume, demute it, and give priority.

I am using the the code bellow to fetch the data from the audio codec at using the left justified mode at a frequency of 48KHZ in an 8 bit form; but it doesn't seem to work.

Could any one give me a hand please. I am struggling with this codec for more than a week. is there any thing wrong with it or is it soemthing else?

thanks in advance.

library ieee;

use ieee.std_logic_1164.all;

use ieee.numeric_std.all;

entity digital_audio_interface is

port(

clk , reset : in std_logic;

adc_data_out : out std_logic_vector(7 downto 0);

m_clk, b_clk, lr_clk : out std_logic;

adcdat : in std_logic;

load_done_tick : out std_logic);

end digital_audio_interface;

architecture arch of digital_audio_interface is

constant m_dvsr: integer := 2;

constant b_dvsr: integer := 3;

constant lr_dvsr: integer := 5;

signal m_reg , m_next : unsigned(m_dvsr-1 downto 0);

signal b_reg, b_next : unsigned(b_dvsr -1 downto 0);

signal lr_reg, lr_next : unsigned(lr_dvsr - 1 downto 0);

signal neg_lr_clk : std_logic;

signal adc_buf_reg, adc_buf_next : std_logic_vector(15 downto 0);

signal lr_delayed_reg, b_delayed_reg: std_logic;

signal load_tick, m_12_5m_tick: std_logic;

signal b_neg_tick, b_pos_tick : std_logic;

signal data_out_reg, data_out_next : std_logic_vector(7 downto 0);

begin

-- clk signals for codec digital audio interface

--registers

process(clk, reset)

begin

if reset ='1' then

m_reg <= (others => '0');

b_reg <= (others => '0');

lr_reg <= (others => '0');

adc_buf_reg <= (others => '0');

b_delayed_reg <= '0';

lr_delayed_reg <= '0';

data_out_reg <= (others => '0');

elsif( clk'event and clk = '1') then

m_reg <= m_next;

b_reg <= b_next;

lr_reg <= lr_next;

adc_buf_reg <= adc_buf_next;

b_delayed_reg <= b_reg(b_dvsr - 1);

lr_delayed_reg <= lr_reg(lr_dvsr -1);

data_out_reg <= data_out_next;

end if;

end process;

-- codec 12.5 mhz m_clk (master clock) ideally it should be 12.288

m_next <= m_reg + 1;

m_clk <= m_reg(m_dvsr -1);

m_12_5m_tick <= '1' when m_reg=0 else '0';

-- b_clk (m_clk / 8 = 1.5 mhz)

b_next <= b_reg + 1 when m_12_5m_tick ='1' else b_reg;

b_clk <= b_reg(b_dvsr - 1);

b_neg_tick <= b_delayed_reg and (not b_reg(b_dvsr - 1));

b_pos_tick <= (not b_delayed_reg) and b_reg(b_dvsr - 1);

-- adc/dac_lr_clk (dac_lr_clk/ 32 = 48 khz)

lr_next <= lr_reg + 1 when b_neg_tick = '1' else lr_reg;

lr_clk <= lr_reg (lr_dvsr - 1);

neg_lr_clk <= lr_reg(lr_dvsr-1);

--completion of one mono sound

load_tick <= ( (lr_delayed_reg)) and (not (lr_reg(lr_dvsr - 1)));

load_done_tick <= load_tick;

adc_buf_next <= adc_buf_reg(14 downto 0) & adcdat when (b_pos_tick = '1' and neg_lr_clk = '1') else

adc_buf_reg;

adc_data_out <= data_out_reg(15 downto 8);

end arch;

Altera_Forum · ‎06-14-2012

Hello everyone,

I realize the mistake was not in this code, data is fetched at the rate expected meaning 48 Khz.

I used a downsampler to reduce the sampling rate into 8 Khz. that was the problem.

Altera_Forum · ‎09-12-2013

Hello studmad,

i need to store the digtal data from Codec into memory, can you help me out.