DSP Builder FIFO

[Finees]

Hi Intel team,

I am supporting a customer on a DSP Builder project on MatLab R2022a. However, we need a FIFO block that works with two clocks, one for reading and one for writing, i.e. a dual clock FIFO.
At the moment, I have only found a single port FIFO block as described in the following link.
https://www.intel.com/content/www/us/en/docs/programmable/683337/23-3/fifo.html

Could you suggest any block with these characteristics?

Thank you

[Kshitij_Intel]

Hi,

Currently, we don't have the Dual Clock FIFO in the DSP builder block.

Thank you,

Kshitij Goel

[Finees]

Hi K**bleep**ij Goel

Thanks for your response.
I know that HDL Coder generates HDL code from MATLAB functions, Simulink models (https://www.mathworks.com/help/hdlcoder/getting-started-with-hdl-coder.html).

I was wondering if there is a function that converts HDL code (VHDL or Verilog) into a Simulink block or something similar, as I have Verilog code from a dual clock FIFO memory that I would like to include in a Simulink model.

Regards,

[Kshitij_Intel · Accepted solution]

Hi,

Yes, you can import the HDL. Please use the 16.2.1. HDL Import (intel.com).

It will solve your problem.

Thank you,

Kshitij Goel

[Finees]

Hi,

Thanks for the recommendation. This is useful for me.
I have implemented some Verilog examples and imported them with the HDL Import function and they worked.
On the other hand, I have implemented a Verilog example of a dual clock FIFO memory and tried to import it, but it gives me error:

Is there anyway to use two clocks in general in DSP? DSP builder does not provide any provision for clock to any of its components. It takes the default clock which one sets in the control block.

Thank you,

Finees

[Kshitij_Intel]

Hi,

Yes, that will work as a system clock (Maximum Clock). the write clock and read clock will be your normal 1-bit signals and the inputs to it is like clocks, you want to give.

You can share your example design. I will take a look and check how it can be done as per your requirements.

Hope this helps.

Thank you,

Kshitij Goel

[Finees]

Hi,

Regarding of your last comment I'm a bit confused: "Yes, that will work as a system clock (Maximum Clock). the write clock and read clock will be your normal 1-bit signals and the inputs to it is like clocks, you want to give." 

Are you referring to the write and read clock signals in the FIFO when I tried to import from Verilog to the simulation block?

Thanks,

Finees

[Kshitij_Intel]

Hi Finees,

Yes, it is write clock and read clock signal in the FIFO.

Thank you,

Kshitij Goel

[Kshitij_Intel]

Hi,

As we do not receive any response from you on the previous answer that we have provided. Please login to ‘https://supporttickets.intel.com’, view details of the desire request, and post a response within the next 15 days to allow me to continue to support you. After 15 days, this thread will be transitioned to community support. The community users will be able to help you on your follow-up questions.

Thank you,

Kshitij Goel