DisplayPort Intel® IP on Stratix 10 FPGA

[DZuck1]

Does anyone know if the DisplayPort Intel® IP supports the Stratix 10 FPGA (in specific v1.4)? The Intel website does not have the Stratix 10 listed at all but I see that there is a DisplayPort Intel® Stratix 10 FPGA IP Design Example User Guide https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/ug-dex-s10-dp.pdf

[Vicky1]

Hi, The DisplayPort Intel IP v1.4 doesn`t support the Stratix 10 FPGA refer the link below for v1.4, https://www.intel.com/content/www/us/en/programmable/products/intellectual-property/ip/interface-protocols/m-alt-displayport-megacore.html The support for Stratix 10 FPGA is added in DisplayPort IP v18.1 refer Table 1. from the link below, https://www.intel.com/content/www/us/en/programmable/documentation/hco1421697808363.html#vge1525422597006 Regards, Vikas

[DZuck1]

Thanks Vikas.

Does the DisplayPort IP v18.1 core for Stratix 10 FPGA support the faster 8.1 Gbps per lane (aka HBR3)?

[Vicky1]

Hi,

I think data link support for HBR3(8.10Gbps) is available for for Intel Arria10 & Cyclone 10GX devices only.

Refer Table 4. from the link below,

https://www.intel.com/content/www/us/en/programmable/documentation/hco1421697808363.html#vaj1537373512792

Regards,

Vikas

[DZuck1]

Thank you for your reply. It looks like the support for HBR3 is only in Quartus Prime Pro, is that correct? Are there any plans to support it in regular Quartus Prime?