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Qsys Testbench Simulation Package Descriptor (.spd) file does not exist

I am trying to simulate Nios 2 design with a floating point unit. I was able to instantiate Nios 2 processor, read inputs from FPGA and produce outputs. Now, I am trying to run a simulation. I understand that process of simulating Nios 2 processor follows different path than hardware simulation. I have a test bench written in Verilog, see code below:

`timescale 1 ps / 1 ps     module fpu_test2_top_tb();   reg [9:0] in1, in2; wire [9:0] out1; reg clk; fpu_test2_top uut( .clk(clk), // clk.clk .in1(in1), // in1.export .in2(in2), // in2.export .out1(out1) // out1.export ); always begin clk = 1; #10; clk = 0; #10; end initial begin #11; in1 = 7; in2 = 2; #1; $display("output = %d", out1); end // always @(negedge clk) // begin // #1; // $display("output = %d", out1); // end endmodule

I can run this test bench from Quartus using ModelSim. However, I don't get output from the processor. I think I have to run Nios 2 simulation out of Eclipse by first generating simulation .elf file. I went in to BSP editor and enabled "enable_sim_optimize"


Then generated BSP package and build both bsp project and application in eclipse itself. I have simulation elf file generated now

However, when I right click on application in Eclipse Run as -> Nios II ModelSim I get following error

Does anyone know how to simulate system that involves Nios II processor? What am I doing wrong here? How can I generate *.spd file?

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For NIOS similation, you can refer to this document and review those steps, 3.11. Running a Nios II System with ModelSim