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Hi ,
How to use fPLL with core mode for Arria10? We don't need transceiver in our design, just need fPLL for fractional clock output. but USRCLK used as a general purpose IO is not feeded by a free running clock in our board design. Do fPLL must be calibration with USRCLK even though used as a core mode PLL? From documents ug-01149, "Timing analysis is not supported for the Arria 10 fPLL used as a core PLL." Is it really? Thank you!Link Copied
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set_global_assignment -name AUTO_RESERVE_CLKUSR_FOR_CALIBRATION OFF

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