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Altera_Forum
Honored Contributor I
934 Views

Driving FPGA -> Host DMA with PCIe (hard IP in Cyclone IV)?

Hello all, 

 

I am trying to port an existing design which uses a PCI interface to a new board which uses the PCIe interface. 

 

Driving a DMA transfer on PCI was fairly simple, you write to the output then read a status bit until it's set/cleared to let you know it's gone. 

 

I can't find any information on how to do the same thing with the PCIe interface.  

 

If I write a burst of 32* 32 bit words, how do I know when I can write the next block? 

 

Thanks for any pointers, 

 

 

Nial.
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6 Replies
Altera_Forum
Honored Contributor I
44 Views

I forgot to say that I'm using the Avalon MM interface. 

 

 

Nial.
Altera_Forum
Honored Contributor I
44 Views

You should be able to do the exact same thing as PCI in PCIe. 

You can use bar access to read out the status of the DMA. 

or use interrupt.
Altera_Forum
Honored Contributor I
44 Views

 

--- Quote Start ---  

You should be able to do the exact same thing as PCI in PCIe. 

You can use bar access to read out the status of the DMA. 

or use interrupt. 

--- Quote End ---  

 

 

 

In the PCI core there's a Control Register at offset 0x306C, bit 5 of this tells 

you when the data you've written to the Tx port has been sent. 

 

I can't find any description in the PCIe User Guide of any similar register 

or mechanism. 

 

 

Nial.
Altera_Forum
Honored Contributor I
44 Views

I'm sorry, I'm not sure about register inside of the core. 

But as I mentioned, you can use bar access to DMA status register directly and be able to read out its status. 

 

Accessing to the PCI register is also using in band, so I think it should be same performance.
Altera_Forum
Honored Contributor I
44 Views

 

--- Quote Start ---  

I'm sorry, I'm not sure about register inside of the core. 

But as I mentioned, you can use bar access to DMA status register directly and be able to read out its status. 

 

--- Quote End ---  

 

 

_Which_ DMA status register? 

 

I'm not using the DMA controller, my logic drives a DMA tansfer directly. 

This has to be able to read the DMA status but I can't see anything in the  

PCIe user guide about a 'finished the transfer' register. 

 

 

Nial.
Altera_Forum
Honored Contributor I
44 Views

 

--- Quote Start ---  

_Which_ DMA status register? 

I'm not using the DMA controller, my logic drives a DMA tansfer directly. 

This has to be able to read the DMA status but I can't see anything in the  

PCIe user guide about a 'finished the transfer' register. 

 

Nial. 

--- Quote End ---  

 

 

Bump. 

 

Has no-one else driven DMA transfers over the PCIe core from their own logic? 

 

How do you know when you can write the next burst? 

 

Thanks for any pointers, 

 

Nial.
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