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Honored Contributor I
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TSE by Using System Console on DE2-115

Hi, 

 

I'm trying to test on a DE2-115 Terasic board, the TSE reference designs available on AlteraWiki: by using system console, for RGMII or MII interfaces, in Forward loopback mode. 

 

Designs are targetted for Arria II and Stratix IV chips, so I have modified both designs to target Cyclone IV chip (which is on the Terrasic board). When compiling designs, I encountered no problem under Quartus II (v11.0). When using System Console, it doesn't work: data are not sent/received through MII or RGMII interfaces (MDIO link is ok). 

 

I made some traces in tcl scripts in order to see what happens. It seems to be stucked at sending packets: in eth_gen_mon.tcl file:  

while {$receive_ctrl_status != 0x00000004} { 

set receive_ctrl_status [master_read_32 $jtag_master $AddressOffset 1]; 

set receive_ctrl_status [expr {$receive_ctrl_status & 0x00000004}]; 

 

 

Does anybody have tested these designs ? 

 

I would be very nice, if somebody could help me solving my problem. 

 

Many thanks in advance.
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Honored Contributor I
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Hi, I can't help you with console and loopbacks. But i have gotten ethernet working on the DE2-115. 

 

Two forum topics i had a few months ago document what i used to learn about ethernet. I have created working ethernet using the Nios Simple Socket Server example. One post contains the bare minimum code modification to port the example to the DE2-115. 

 

With that code you'll have some simple working ethernet immediately. Hopefully that code and posts can help you get started. 

 

http://www.alteraforum.com/forum/showthread.php?t=28577 

http://www.alteraforum.com/forum/showthread.php?t=28837 

 

Good Luck
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Honored Contributor I
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Hi, 

 

thank you for your answer. 

 

As you, I had a look at web server demo design given with DE2-115 board, but it is too complex for just testing ethernet link. I also read a lot of documents, among them, the TSE Megacore of course. I spent a long time testing this design, but it's not easy and I can not use it "as is" in a further design, That's why I'm looking for a very simple design (no web server or something like this), without NIOS if possible (that's why both designs on Wiki with system console, seem to be the easier ones ... but they don't seem to work correctly). 

 

My goal is to validate ethernet link in RGMII mode at all speeds (Gb, 100M and 10M), with Marvell PHY and Cyclone IV chip.  

I also tried Altera reference designs for CIII boards but without success. So, I will have a look at yours.
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Honored Contributor I
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The only other thing I know of is the nios Udp offload example; just google it, it's on altera wiki. I'm struggling with that at the moment. The idea of the example is to have both hardware control of the TSE Mac and with the nios. Perhaps you can gain insight on how to just use hardware by looking at that example. But I think the simplest is the SSS example.  

 

My next goal is to get Udp offload example going. If you figure out a way to get 100mbps or more without using c code on nios please let me know.
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Honored Contributor I
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How have you gone?

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Honored Contributor I
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Hi, 

 

first of all, I am really sorry for the delay of my answer :oops:. 

 

Since two weeks, I tried to use your design as others concerning TSE with NIOS, but I didn't manage to use them in a good way. So I gave up with these reference designs.  

I saw that Altera put a new reference design with RGMII (AN647). It seems that this design replaces the one I found on the Wiki. So, I modified it in order to target it for the Cyclone IV on DE2-115 board. I have more success with this new reference design as packets are now sent ... but some of them are only receive and the results are still random for the moment: for example, when configuring sending 10000 packets in the ethernet monitor, the number of received packets is sometimes 12864, sometimes 11796, sometimes another number, sometimes only 1 and then the design is stucked. But this is the same when configuring the link at 10, 100 or 1000Mbps. 

 

So, I guess I have a problem of timing in my design, but I don't see which one for the moment. 

 

This design uses system console and not any Nios for generating and monitoring ethernet packets. You only use Verilog code and TCL scripts for testing all possibilities. 

 

If you have the same DE2-115 board and would like to try this design, it would be nice. Of course, if I manage to use it in a right way, I will let you know.
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Honored Contributor I
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I'm trying to do similar work with the DE2-115, could you post a link to the new reference design as well as what changes you had to make? Also if you could post your code I would be happy to look it over to see if what my attempts to get my project working can help you.

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Honored Contributor I
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Hi, 

 

the reference design can be found here on Altera web site. I'm still unable to post a link at this time, so please go the "Literature page", then choose the "Application Notes" link. It is the first application note, referenced AN647. 

 

I used the design targetted for Arria II and I modified it in order to use it on a Cyclone IVE (the one on the Terasic board). Please find attached my design. 

 

The design seems to work when including a signal tap module, but it is still stucked without this signal tap module. So, I am almost sure that it is about a problem of timing.
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Honored Contributor I
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Hi Rick, 

Is this still youyr latest code? 

I weas going to have a look because i'm trying to get the "Nios UDP Offload Example" style UDP bypass up and running. I'm having trouble getting my HDL packets to the TSE MAC correctly. It works for the TCP connection extablished via uCos on the Nios. 

I was thinking perhaps two birds with one stone?
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Honored Contributor I
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Hi AsValdr, 

 

yes, as far as I remember (it was holidays time ;) ) this is my last code. Maybe I made some modifications in timing constraints file (*.sdc), but no changes in source files or tcl files.
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