FPGA Intellectual Property

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FPGA Intellectual Property

Discussions

SDI transmitter serial output problem

Altera support request 11218245 - Reinstate the auk_ddr_hp_controller.vhd core li

DSP Builder fft megacore Error

Custom IP Simulation in ModelSim

custom Avalon MM master questions.

DDR3 memory with Uniphy is SLOW

Verification of Stratix V Hard IP for PCI Express Using Avalon-MM Interface with DMA

ALT PLL error

altera FFT

Registers

Cyclone V GT, Custom PHY IP Core

CIC IP Core in Quartus 15.1 for 5CSEBA5U23

Cannot generate rapid io ip core

Turbo Megacore

about timing problem of FIR II IP

Featured Content

Can a 1000mbps RGMII TSE communicate with a 100mbps PC?

Critical Warning: PLL clock

H-Tile PCIe Streaming Hard-IP - constrain application logic clocked by coreclkout_hip

Re: Can a 1000mbps RGMII TSE communicate with a 100mbps PC?

Re: Can a 1000mbps RGMII TSE communicate with a 100mbps PC?

Error reported by S-function 'mip_control' in Control Block

Re: Altera Simple Dual Port RAM -- Read cycle latency