EMIF IPSupport

[DillipriyaP]

When simulating the EMIF IP with the example design, we encountered an issue where there was a random latency between the read_enable and read_valid signals. We couldn't identify the reason for this behavior. Additionally, we replicated the design on hardware using inputs provided through the system console, and we observed the same issue. Could you provide clarity on what parameters might be introducing this random delay between read_enable and read_valid.

[sstrell]

Questions:  What target device is this?  What are your parameter settings for the IP?  What is the "ready" signal you are tapping?  Is that supposed to be the Avalon waitrequest signal (which you should be tapping if you're not to know when the interconnect is ready to receive a read command).  Remember, if waitrequest is low, you have to hold the read or write command on the bus until waitrequest goes low.  You say this is the traffic generator so it should honor that, but it would be good to see in Signal Tap.

[AdzimZM_Intel]

Hi,

We sincerely apologize for the inconvenience caused by the delay in addressing your Forum queries. Due to an unexpected back-end issue in our system, your Forum case, did not reach us as intended. As a result, we have a backlog of cases that we are currently working through.

Please be assured that we are doing everything we can to resolve this as quickly as possible. This will take some time, and we appreciate your patience and understanding during this period of time. Thank you again for your patience and understanding, and we are committed to provide you with the best possible support.

The read burst transfer would expect to get the delay before the readdatavalid is coming after the waitrequest is triggered.

You may try to improve the controller efficiency by following the suggestion in the Agilex EMIF IP UG.

https://www.intel.com/content/www/us/en/docs/programmable/683216/23-2-2-7-1/improving-controller-efficiency.html

Regards,

Adzim

[DillipriyaP]

Thanks for your information we solved the issue.

[AdzimZM_Intel]

I’m glad that your question has been addressed, I now transition this thread to community support. If you have a new question, feel free to open a new thread to get the support from Intel experts. Otherwise, the community users will continue to help you on this thread. Thank you.