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Enabling interrupts in Cyclone 10 GX PCIe endpoint (Avalon-MM Bridge Register space?)


Trying to get interrupts working on a Cyclone 10 GX design, using the PCIe Avalon-MM endpoint.   I have several interrupt sources connected up to the PCIe core in Platform Designer, but so far neither legacy nor MSI interrupts are making it to the host CPU (at the root complex).

Section 6.7 of the PCIe core docs shows the Avalon-MM Bridge Register Descriptions, which include interrupt enable and status registers.  Clearly, it would seem that the interrupt enables would need to be set in order to allow the interrupts to go through.  We are having trouble working out the details, though.

  1. Does the interrupt enable register default to 0?  That is our guess, which would explain why we're not getting any interrupts.
  2. Exactly how is the root complex supposed to access this register space?  Is it I/O space?  Do I need to allocate a BAR for this?  I can't figure out what I need to initialize in order to make this work.
  3. This is Intel-specific stuff, right?  None of the standard drivers seem to do anything in this area.
  4. Table 49 on page 75 shows the interrupt status register at address 0x0060.  This value disagrees with the register map on the previous page (Table 48).   Table 51 shows the Interrupt Vector Register also listed as being at address 0x0060, both can't be right.  And finally the Interrupt Vector Register is not shown in the register map.  The docs all seem a bit confused here.
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