I am trying to work with the following design example.
I am able to compile the design for our Stratix 10 MX Board (Device :
Quartus Version : 21.2
When I try to download the bitstream, it stops around 85%, giving the following error:
Error(18950): Device has stopped receiving configuration data
Error(18948): Error message received from device: Device is in configuration state.
Error(209012): Operation failed
Can anyone let me know, what can be the solution for this ?
P.S: I am able to download other basic example involving PCIe endpoint.
May I know if your refclk is stable for the HBM2 and PCIe interface? You may refer to https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/hb/stratix-10/ug-s10-config... Table 53 on the debug checklist for the configuration issue.
Thanks for the reply.
I was able to solve the issue by assigning the correct pin numbers to reference clocks of HBM.
I was able to build the Qsys design with MCDMA IP interfaced with HBM Controller through AXI bridge. ( I have modified the example design PCIe + DDR + HBM2. I have replaced PCIe endpoint IP with MCDMA IP).
I am able to build and program the design successfully using Quartus 21.3 version.
During software test, system is not able to work with burstcount greater than 1. I have enabled burstcount greater than 1 option during HBM Controller generation. I have given it as 128 (max is 256).
Does HBM controller with AXI interface works with burst count greater than 1 ?
Yeah, I have checked that PCIe IP is sending the signals to HBM controller inputs.
Wanted to check with you:
the design example above, can the design be made to work with burst count > 1.
Will the design work if increase the burst capability of clock crossing bridge and HBM controller ?
If you look at the user guide, you will observed that the HBM can only support burst count of 1. Below is the information from the document.
Burst length adaptation
The Gen3 x16 IP Write Data Mover (WRDM) and Read Data Mover (RDDM) Avalon-MM interfaces are bursting masters that issue Read/Write transactions in burst mode (the maximum burst count supported is 8). However, the HBM Controller AXI4 slave only supports single-burst transfers (burst length of 1). To resolve this, the maximum burst size in the Avalon-MM clock crossing bridges is set to 1.