Error(18694) with LVDS SERDES IP

[J314]

The planned design is to be implemented on a Cyclone 10GX and compiled with Quartus Prime Pro 22.4. In the design an external clock at I/O bank 2L is provided. I want to communicate with LVDS signals via I/Os of the I/O banks 2A, 2J, 2K, 3A. The plan is to use the LVDS SERDES IP core for this, with an external PLL. The design now consists of a first IOPLL, which converts the external reference clock from bank 2L into several system clocks of different frequencies. One of these clocks is used for the refclk signal of the second IOPLL, that drives the LVDS SERDES IP (PLL cascading). So far so good... But when I compile the design, I get the following error message:

"Error(18694): The reference clock on PLL <name of second IOPLL>, which feeds an Altera LVDS SERDES IP instance, is not driven by a dedicated reference clock pin from the same bank. Use a dedicated reference clock pin to guarantee meeting the LVDS SERDES IP max data rate specification."

I have now already found/read different reasons, causes and solutions in several posts:

1. Only a bug in Quartus version 19.4, should be fixed from version 20.1 (Error(18694): The reference clock on PLL... (intel.com))
2. A dedicated reference clock should be used for the second IOPLL (How to workaround the ERROR ID:18694 - Intel Communities)
3. An error that occurs from version 18.1 upwards that can be worked around with a QSF assignment (Error (18694): The reference clock on PLL... (intel.com))
4. An older version of Quartus should be used (Solved: LVDS SERDES reference clock enforcement change in 18.1 - Intel Communities)

Post 1 was not helpful as I am using version 22.4 and the bug seems to still be there. Post 2 cannot be implemented because only the one reference clock is present and furthermore it is not in the same IO bank as the I/Os to be controlled. The solution from post 3 was also not successful and to use an older Quartus version, as suggested in post 4, is unfortunately also not possible.

Now I'm not sure if I'm trying to implement an impossible design, or if there is a solution after all, which I either didn't take from the posts correctly, or which isn't listed in the posts yet.

Thanks for your help

[FvM]

Hello,
above quoted solutions 1 and 3 are apparently erroneous. Nothing related to error(18694) has been fixed in QPP 20.1.

As for a possible solution, see my comment in
https://community.intel.com/t5/FPGA-Intellectual-Property/SERDES-IP-not-compiling-after-migrating-to-Quartus-Pro-23-1/td-p/1448743

As long as no solution is provided by Intel, I'd use QPP18.0 (solution 4) for existing designs that can't implement solution 2.

[AqidAyman_Intel]

Hi,

You may refer to this handbook, https://www.intel.com/content/www/us/en/docs/programmable/683775/current/guideline-lvds-reference-clock-source.html.

It mentioned that if the reference clock input comes from other I/O banks, this source must come from another I/O bank and not from other sources such as IOPLL IP.

Regards,

Aqid