Error compiling model using DSP Builder

[ThangND]

Hi all, I'm having some problems when compiling my design with Altera DSP Builder (my current version is v16.1 and MATLAB R2016a). It has been for months since I started building my projects with Altera DSP Builder software and compiling the HDL design by using the SignalCompiler blockset. Everything has worked fine until today. This morning when I compiled my simulink design as usual, the SignalCompiler window shows me an error while analyzing model: 

DSP Builder Error

Could anyone show me how to fix this error ? Thanks. 

Update: I found the errors in the Avalon-MM Slave block, which happened to miss the connected wire to the read data signal. This block is appeared to be automatically disconnect the already-connected wire occasionally and I don't know why. 

[Kshitij_Intel]

Hi,

Can you please share the model.

Thank you

Kshitij Goel

[Kshitij_Intel]

Hi,

As we do not receive any response from you on the previous question that we have provided. Please login to ‘https://supporttickets.intel.com’, view details of the desire request, and post a response within the next 15 days to allow me to continue to support you. After 15 days, this thread will be transitioned to community support. The community users will be able to help you on your follow-up questions.

Thank you

Kshitij Goel