FPGA Intellectual Property
PCI Express*, Networking and Connectivity, Memory Interfaces, DSP IP, and Video IP
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Error while executing the design - Fiiting(Plce error)

mrama13
Principiante
1.062 Vistas

Error Description:

Main error:

Error(14566): The Fitter cannot place 1 periphery component(s) due to conflicts with existing constraints (1 HSSI_RX_CHANNEL_CLUSTER(s)).

 

Sub errors:

Error(175001): The Fitter cannot place 1 HSSI_RX_CHANNEL_CLUSTER, which is within Generic Component fam_system_pcie_avmm_m.            

 

Error(16234): No legal location could be found out of 1 considered location(s).  Reasons why each location could not be used are summarized below:

 

Error(20196): Location(s) already occupied and the components cannot be merged. (1 location affected)

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2 Respuestas
CheePin_C_Intel
Empleados
1.046 Vistas

Hi,


As I understand it, you observe some issue with Fitter placement. By merely looking at the error messages, it seems like your design has some placement violation. It may be due to limited resource or placement rule violation. To facilitate further debugging, would you mind to further elaborate on the following:


  1. What is the specific device and Quartus version that you are using?
  2. What is the specific IPs that you are using ie Native PHY, PCIe HIP and etc?
  3. Mind share with me high level diagram of your placement within a XCVR bank ie XCVR channel, TX PLL?


Please let me know if there is any concern. Thank you.


CheePin_C_Intel
Empleados
1.023 Vistas

Hi,


Just would like to follow up with you on this. Thank you.


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