I am an algorithms engineer.
I want to use a 2048 bins FFT, streaming mode, block fixed point, 16 bit for both twiddle and data.
I am running the Matlab model trying to understand the behaviour and I am truly puzzled.
For example it seems to me that the output is much less than 16 bits.
I try for example the following signal
I0 = 32767, I1-I2047, Q0-2047 = 0.
I get output IOut0 - IOut2047 = 1024, with scaling.
If I change I0 to 32760, I get IOut0 - IOut2047 = 2048 (lower scaling).
I can't understand this behavior.
I don't understand why I won't receive Iout = 32767 or close?
As I understand it, you have some inquiries related to FFT IP. To ensure we are on the same page, just would like to check with you on the following:
The Matlab matches the fpga simulations. So that's not a "hardware" problem.
I am trying to understand the rational of the results I get - the main issue - why the output precision is usually much less than the 16 bits of input.
Thanks for your clarification that the Matlab result matches the FPGA simulation. Based on this, it seems like the observation that you are seeing is expected behavior of the FFT under your specific configuration. This seems to be trending towards FFT theoretical behavior and I would like to get further information from you to see if find any clue for your inquiry:
1. Would you mind share with me the FFT .ip file generated by Quartus so that I can have a better understanding of your configuration?
2. What is the Quartus version of FPGA device that you are using?
3. Would you mind to share with me the Matlab simulation or the FPGA simulation so that I can have a better understanding on the output precision observation that you are referring to?
4. Please feel free to let me know the Matlab version as well as the Modelsim version that you are using for simulation.
Please let me know if there is any concern. Thank you.