FIFO problem with reading

[AAgan1]

Here there Intel community,

I'm having problem with a DCFIFO of input width of 32bits and 128 width of output from Quartus 18.1, I have simulated this DCFIFO with ModelSim which came with the installation,

I'm writing in a frequency of 159.375 MHz generated by a PLL and reading in a frequency of 232.33 MHZ generated by a DDR controller (EMIF), the writing is made constant, writing in a bunch of data and reading one by one, you can see in the image that the writing s_write_fifo_enable_in and reading in the Input_Fifo_Read_Enable you can se that the rd_data_count_sig which is the counter of the "rdusedw" of the DCFIFO, you can see that the DCFIFO is not behaving normally, and create those holes in the counting and it seems that the DCFIFO is losing data, the output data of the DCFIFO goes to a DDR and it is a video frame and in the output I can see that the image sometimes has this lines that does not correspond to the actual image.

If any one can help me about this? or give me some hints, in the simulation if you read instead of one by one like that and read a bunch the DCFIFO acts normal.

Input_FIFO_1 is the part of the simulation and Input_FIFO_2 is a zoom of one of the red circles.

Thanks.

[RichardTanSY_Intel]

Hi,

I apologize for the delay in response. This case has been idle for some time.

Not sure have you found a solution? Do you need further help on this case?

[AAgan1]

No I haven't found anything, that happend in simulation but I'm not sure if it happens in real hardware, in simulation I'm using a stub FIFOS to check my logic.

All my logic seem to be working OK. I'm dealing with a problem in a DDR IP controller (EMIF), I have this config: INPUT_FIFO->DDR->OUTPUT_FIFO, I did a lot of ways of writing, this are the scenarios:

1. I write once to the bank 0 and then read to the bank 0 all the time.
2. I write once to the bank 0 wait (100 ms until 1 s) and then read to the bank 0 all the time.
3. I write and read changing in a different way as a circular buffer between Bank 0, Bank 1 and Bank2.
4. Among others ways of the logic.

The noise stuff seems to be the data from another bank, like if the image overlap in that places. I have change a lot of the code and made a lot of test, I have eliminated a lot of possibles causes and in simulation seems that the my logic works ok, the only thing that I can think of is the DDR controller (EMIF), do you know if there is something or an idea?, I'm using the "Cyclone 10 GX FPGA Development Kit".