[FIFO]

[amildm]

Hi,

I'm about the "Asynchronous clear" signal in the FIFO IP - what's its functionality? What does it actually clear?

Once this signal is asserted, does it bring both the read and write pointers to point to the same FIFO entry? Should this be the first entry ?

 

Thanks!

[SyafieqS · Accepted solution]

Hi Dmitry,

The FIFO Intel® FPGA IP core supports the synchronous clear (sclr) and asynchronous clear (aclr) signals, depending on the FIFO modes. The effects of these signals are varied for different FIFO configurations. The SCFIFO supports both synchronous and asynchronous clear signals while the DCFIFO support asynchronous clear signal and asynchronous clear signal that synchronized with the write and read clocks. You may take a look at below link for different scenario and details about async clear

https://www.intel.com/content/www/us/en/docs/programmable/683522/18-0/fifo-synchronous-clear-and-asynchronous.html

https://www.intel.com/content/www/us/en/docs/programmable/683241/21-1/fifo-synchronous-clear-and-asynchronous.html

[Nurina]

Hi Dmitry,

May I know if the above response helps? Can we put this thread to close pending?

Regards,

Nurina

[amildm]

yes, I've already marked the answer as an Accepted Solution, thanks a lot!

[SyafieqS]

I’m glad that your question has been addressed, I now transition this thread to community support. If you have a new question, feel free to open a new thread to get the support from Intel experts. Otherwise, the community users will continue to help you on this thread. Thank you.

p/s: If any answer from community or Intel support are helpful, please feel free to mark as solution and give Kudos.