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Altera_Forum
Honored Contributor I
4,342 Views

Tutorial: Using the USB-Blaster as an SOPC/Qsys Avalon-MM master

Hi all, 

 

I've put together a tutorial on how to use the Altera JTAG-to-Avalon-MM master and Altera Verification IP Avalon-MM BFM Master under both SOPC builder and Qsys. 

 

http://www.ovro.caltech.edu/~dwh/correlator/pdf/altera_jtag_to_avalon_mm_tutorial.pdf (http://www.ovro.caltech.edu/%7edwh/correlator/pdf/altera_jtag_to_avalon_mm_tutorial.pdf

http://www.ovro.caltech.edu/~dwh/correlator/pdf/altera_jtag_to_avalon_mm_tutorial.zip (http://www.ovro.caltech.edu/%7edwh/correlator/pdf/altera_jtag_to_avalon_mm_tutorial.zip

 

The tutorial walks the user through the creation of an SOPC or Qsys system design, and provides scripts that automate the re-generation of the system. The tutorial shows how to simulate using Modelsim-ASE, and shows how to communicate with the hardware using System Console, quartus_stp, and then how to run a TCP/IP server under System Console or quartus_stp, and then communicate with that server from client code written in Tcl/Tk (a simple GUI) and a command-line C interface. 

 

Let me know if you like it, or have feedback/suggestions on how to improve the document. 

 

Cheers, 

Dave
0 Kudos
118 Replies
Altera_Forum
Honored Contributor I
367 Views

Very interesting reading!

Altera_Forum
Honored Contributor I
367 Views

I created a page on the AlteraWiki. That should make it easier to find. 

 

http://www.alterawiki.com/wiki/using_the_usb-blaster_as_an_sopc/qsys_avalon-mm_master_tutorial 

 

Any idea how I can add search keywords to the wiki? It would be nice if search terms like "JTAG-to-Avalon-MM master" linked to the wiki page. 

 

Cheers, 

Dave
Altera_Forum
Honored Contributor I
367 Views

If I remember correctly the keywords derived from the page title.

Altera_Forum
Honored Contributor I
367 Views

 

--- Quote Start ---  

If I remember correctly the keywords derived from the page title. 

--- Quote End ---  

 

 

And the title is non-editable once you create the page ... oh the joys of wiki's :) 

 

I see a block with links to "Categories" on the bottom of some pages. Any idea on how to add something like that? I'll see if I can find a wiki page that has some instructions. 

 

Thanks! 

 

Cheers, 

Dave
Altera_Forum
Honored Contributor I
367 Views

These are the categories to choose from: http://www.alterawiki.com/wiki/special:categories 

 

You can add your page to one of those categories by clicking the little [c] icon in the editor, this page has more details: http://www.alterawiki.com/wiki/help:editing#create_a_new_page
Altera_Forum
Honored Contributor I
367 Views

 

--- Quote Start ---  

 

You can add your page to one of those categories by clicking the little [c] icon in the editor 

--- Quote End ---  

It appears to be broken. Rather than popping up a list of categories to select from, it pops up a window with an HTML error message. 

 

I've attached the error message generated from the Sandbox test page, so its not something specific to the page I created. I don't see any links on the Wiki pages to anyone who might be able to help with this. Suggestions? 

 

Cheers, 

Dave
Altera_Forum
Honored Contributor I
367 Views

The wiki category icon is in fact broken. 

 

You can add a category in the wikitext mode manually. Add the following text to the bottom: 

[[Category:Qsys]]
Altera_Forum
Honored Contributor I
367 Views

 

--- Quote Start ---  

The wiki category icon is in fact broken. 

 

--- Quote End ---  

 

 

Does anyone know how to fix it? 

 

 

--- Quote Start ---  

 

You can add a category in the wikitext mode manually. Add the following text to the bottom: 

[[Category:Qsys]] 

--- Quote End ---  

 

 

Cool! Thanks for editing the page. 

 

Cheers, 

Dave
Altera_Forum
Honored Contributor I
367 Views

I find it very useful tutorial. The explanation throughout the material provides readers a more comprehensive understanding about designing with Qsys, SOPC. I could not generate in Qsys but will try to make it done soon then continue learning whole tutorial. Thanks for your contribution.

Altera_Forum
Honored Contributor I
367 Views

Hi, 

 

I'm following the Altera JTAG-to-Avalon-MM Tutorial, version 1.0 from March 14, 2012. 

I'm using Quartus webedition 10.1 no SP installed. 

I also uses the corresponding free Modelsim version 6.6c 

 

The reason I uses 10.1 is that I have a Cyclone 1 board.  

Cyclone 1 is not supported in Quartus 11 and higher. 

 

I'm following the document and follow the SOPC flow, as QSys is not recommended for this version according to the document 

 

I can follow the document but run into a problem on page 19. 

 

There it says: 

- Run the simulation 

 

--- Quote Start ---  

VSIM> vsim -t ps +nowarnTFMPC sopc_system_jtag_master_tb 

--- Quote End ---  

This gives an error in Modelsim 

 

--- Quote Start ---  

# Loading work.altera_avalon_st_pipeline_base# ** Error: (vsim-3043) c:/temp/altera_jtag_to_avalon_mm_tutorial/hdl/sopc_system/test/sopc_system_jtag_master_tb.sv(122): Unresolved reference to 'jtag_master_inst' in dut.the_jtag_master.jtag_master_inst.# Region: /sopc_system_jtag_master_tb# Error loading design 

Modelsim> 

--- Quote End ---  

When I go to this file and line 122 it says: 

line 117: // -------------------------------------------------------- line 118: // JTAG reset line 119: // -------------------------------------------------------- line 120: // line 121: $display(" * Reset the JTAG controller"); line 122: `VTAP.reset_jtag_state; When I search on VTAP it says at line 36 the following: 

line 36: // Quartus 11.1sp1 line 37: // --------------- line 38: `define VTAP dut.the_jtag_master.jtag_master_inst.jtag_phy_embedded_in_jtag_master.normal.jtag_dc_streaming.jtag_streaming.node line 39: line 40: // Quartus 10.0 line 41: // ------------ line 42: // The component hierarchy is slightly different for Quartus versions line 43: // earlier than 11.1sp1. The sopc_system_jtag_master_tb.do script line 44: // JTAG master nodes also change names. line 45: //`define VTAP dut.the_jtag_master.jtag_master.normal.altera_jtag_avalon_master_pli_off_inst.the_altera_jtag_avalon_master_jtag_interface_pli_off.altera_jtag_avalon_master_jtag_interface_pli_off.normal.jtag_dc_streaming.jtag_streaming.node By commenting the 11.1sp1 define (line 38) and un-commenting the 10.0 version (line 45) it works. 

 

(Just sharing information sofar for solving this problem) 

 

When I then do the next line  

 

--- Quote Start ---  

 

VSIM> do $TUTORIAL/hdl/sopc_system/scripts/sopc_system_jtag_master_tb.do 

 

--- Quote End ---  

it gives an error on the jtag_master signals: 

# ** Error: (vish-4014) No objects found matching '/sopc_system_jtag_master_tb/dut/the_jtag_master/master_write'.# Executing ONERROR command at macro c:\temp\altera_jtag_to_avalon_mm_tutorial\hdl\sopc_system\scripts\sopc_system_jtag_master_tb.do line 9# ** Error: (vish-4014) No objects found matching '/sopc_system_jtag_master_tb/dut/the_jtag_master/master_read'.# Executing ONERROR command at macro c:\temp\altera_jtag_to_avalon_mm_tutorial\hdl\sopc_system\scripts\sopc_system_jtag_master_tb.do line 10# ** Error: (vish-4014) No objects found matching '/sopc_system_jtag_master_tb/dut/the_jtag_master/master_address'.# Executing ONERROR command at macro c:\temp\altera_jtag_to_avalon_mm_tutorial\hdl\sopc_system\scripts\sopc_system_jtag_master_tb.do line 11# ** Error: (vish-4014) No objects found matching '/sopc_system_jtag_master_tb/dut/the_jtag_master/master_byteenable'.# Executing ONERROR command at macro c:\temp\altera_jtag_to_avalon_mm_tutorial\hdl\sopc_system\scripts\sopc_system_jtag_master_tb.do line 12# ** Error: (vish-4014) No objects found matching '/sopc_system_jtag_master_tb/dut/the_jtag_master/master_writedata'.# Executing ONERROR command at macro c:\temp\altera_jtag_to_avalon_mm_tutorial\hdl\sopc_system\scripts\sopc_system_jtag_master_tb.do line 13# ** Error: (vish-4014) No objects found matching '/sopc_system_jtag_master_tb/dut/the_jtag_master/master_readdata'.# Executing ONERROR command at macro c:\temp\altera_jtag_to_avalon_mm_tutorial\hdl\sopc_system\scripts\sopc_system_jtag_master_tb.do line 14# ** Error: (vish-4014) No objects found matching '/sopc_system_jtag_master_tb/dut/the_jtag_master/master_waitrequest'.# Executing ONERROR command at macro c:\temp\altera_jtag_to_avalon_mm_tutorial\hdl\sopc_system\scripts\sopc_system_jtag_master_tb.do line 15# ** Error: (vish-4014) No objects found matching '/sopc_system_jtag_master_tb/dut/the_jtag_master/master_readdatavalid'.# Executing ONERROR command at macro c:\temp\altera_jtag_to_avalon_mm_tutorial\hdl\sopc_system\scripts\sopc_system_jtag_master_tb.do line 16 Is this a quartus 10.1 specific error? 

Or is this an error in the defined waves in the do-file? 

 

Rgds, 

Kimberley
TWatt3
Novice
200 Views

​Does anyone know where I can get the zip file for this tutorial?  The original link does not work?

 

 

Thanks.

 

 

 

Altera_Forum
Honored Contributor I
367 Views

Hi Kimberley, 

 

Glad to read that you managed to figure out how to get the tutorial to compile in 10.1. The errors you see from executing the .do file are due to the path changes in the component heirarchy. You can probably fix these errors; in the tutorial on page 18 there is a picture of the Modelsim hierarchy window showing the path to the JTAG node. Use the Modelsim GUI to look at this path name in the version you are using - it will be slightly different - edit the .do file and change the names of the signals that have an incorrect path. Re-run the script a couple of times until you have the names correct, i.e., until Modelsim does not generate a warning. 

 

Altera changes the hierarchy of some components between versions, so its difficult to write a tutorial that works under all versions :) 

 

Another way to use the tutorial, is as a method for learning how to create your own custom SOPC systems. You can use the tutorial and Quartus 11.1sp1 to learn how to create a system, and then use Quartus 10.0 to create your own systems. 

 

Let me know if you have any troubles and I'll try to help. 

 

Cheers, 

Dave
Altera_Forum
Honored Contributor I
367 Views

Hi Dave, 

 

Thanks for the help. 

See attached my modelsim image. 

It's quite different then the image in the document. 

Where can I find the similair signals? 

 

Rgds, 

Kimberley
Altera_Forum
Honored Contributor I
367 Views

Hi Dave, 

 

Another question I have is the following: 

On page 37 I read the sentences:  

 

--- Quote Start ---  

 

“The Tcl fileevent command is critical to the implementation of a Tcl TCP/IP server. Versions of Systems Console earlier than Quartus II version 11.1sp1 did not support the Tcl filevent procedure…” 

 

--- Quote End ---  

 

This would mean that the program won’t run in my quartus 10.1 version? 

Do you have a solution for this? 

 

For example is it possible to split this up? 

Meaning, if I install also quartus 11.1sp1 and run this tcl server/client program from a 11.1sp1 quartus_sh terminal, can I then still communicate to my sopc system generated in quartus 10.1? 

 

Rgds, 

Kimberley
Altera_Forum
Honored Contributor I
367 Views

Hi Kimberley, 

 

--- Quote Start ---  

 

See attached my modelsim image. 

It's quite different then the image in the document. 

Where can I find the similair signals? 

 

--- Quote End ---  

Look back at the code you just edited - line 45  

 

line 40: // Quartus 10.0 line 41: // ------------ line 42: // The component hierarchy is slightly different for Quartus versions line 43: // earlier than 11.1sp1. The sopc_system_jtag_master_tb.do script line 44: // JTAG master nodes also change names. line 45: //`define VTAP dut.the_jtag_master.jtag_master.normal.altera_jtag_avalon_master_pli_off_inst.the_altera_jtag_avalon_master_jtag_interface_pli_off.altera_jtag_avalon_master_jtag_interface_pli_off.normal.jtag_dc_streaming.jtag_streaming.node When you edited the VHDL to change the VTAP path, all you needed to do was edit the .do file to change the same path. I didn't tell you this earlier, as I wanted you to look at the Modelsim hierarchy window so that you would see the correspondence.  

 

Problem solving is how you begin to understand these tools. 

 

Cheers, 

Dave
Altera_Forum
Honored Contributor I
367 Views

 

--- Quote Start ---  

 

Another question I have is the following: 

On page 37 I read the sentences:  

 

This would mean that the program won’t run in my quartus 10.1 version? 

Do you have a solution for this? 

 

--- Quote End ---  

 

 

Of course :) 

 

Read the source code (jtag_server.tcl) ... 

 

# SystemConsole (prior to Quartus 11.1sp1) # # * There is no support for fileevent, so SystemConsole# has to busy loop on one client at a time.# # * If the client closes its connection cleanly via# client_close, then the socket generates an EOF# and the server will wait for the next client.# # * However, if the client disconnection is not cleanm,# eg., the client uses exit or ctrl-C to exit, then# the server does not receive an eof, and it remains# blocked on the dead client connection. New clients,# will not be handled!# # In constrast, when the server is run under# quartus_stp, the server log indicates that a ctrl-C# from a client quartus_stp generates an # 'empty command' followed by 'disconnected'# puts "Handle the client via a blocked read on the socket" while {!} { client_handler $client }  

 

Note that this applies to SystemConsole, whereas quartus_stp (another tool) works fine. 

 

 

--- Quote Start ---  

 

For example is it possible to split this up? 

Meaning, if I install also quartus 11.1sp1 and run this tcl server/client program from a 11.1sp1 quartus_sh terminal, can I then still communicate to my sopc system generated in quartus 10.1? 

 

--- Quote End ---  

 

 

Yes, you can use a newer version of Quartus to communicate with the design after it has been downloaded. The JTAG protocol has not changed between Quartus versions. 

 

Cheers, 

Dave
Altera_Forum
Honored Contributor I
367 Views

Hi Dave, 

 

Thanks for the information. But I think you are a few steps further then I am.  

 

In the post of "November 2nd, 2012, 09:22 AM" I reported that ModelSIM is giving error's on the signals of the JTAG master. 

I think I solved them by changes the "sopc_system_jtag_master_tb.do" file into 

add wave -noupdate -divider {JTAG Master}# add wave -noupdate /sopc_system_jtag_master_tb/dut/the_jtag_master/master_write# add wave -noupdate /sopc_system_jtag_master_tb/dut/the_jtag_master/master_read# add wave -noupdate -radix hexadecimal /sopc_system_jtag_master_tb/dut/the_jtag_master/master_address# add wave -noupdate -radix hexadecimal /sopc_system_jtag_master_tb/dut/the_jtag_master/master_byteenable# add wave -noupdate -radix hexadecimal /sopc_system_jtag_master_tb/dut/the_jtag_master/master_writedata# add wave -noupdate -radix hexadecimal /sopc_system_jtag_master_tb/dut/the_jtag_master/master_readdata# add wave -noupdate /sopc_system_jtag_master_tb/dut/the_jtag_master/master_waitrequest# add wave -noupdate /sopc_system_jtag_master_tb/dut/the_jtag_master/master_readdatavalid add wave -noupdate /sopc_system_jtag_master_tb/dut/the_jtag_master/jtag_master/write_from_the_altera_jtag_avalon_master_packets_to_transactions_converter add wave -noupdate /sopc_system_jtag_master_tb/dut/the_jtag_master/jtag_master/read_from_the_altera_jtag_avalon_master_packets_to_transactions_converter add wave -noupdate -radix hexadecimal /sopc_system_jtag_master_tb/dut/the_jtag_master/jtag_master/address_from_the_altera_jtag_avalon_master_packets_to_transactions_converter add wave -noupdate -radix hexadecimal /sopc_system_jtag_master_tb/dut/the_jtag_master/jtag_master/byteenable_from_the_altera_jtag_avalon_master_packets_to_transactions_converter add wave -noupdate -radix hexadecimal /sopc_system_jtag_master_tb/dut/the_jtag_master/jtag_master/writedata_from_the_altera_jtag_avalon_master_packets_to_transactions_converter add wave -noupdate -radix hexadecimal /sopc_system_jtag_master_tb/dut/the_jtag_master/jtag_master/readdata_to_the_altera_jtag_avalon_master_packets_to_transactions_converter add wave -noupdate /sopc_system_jtag_master_tb/dut/the_jtag_master/jtag_master/waitrequest_to_the_altera_jtag_avalon_master_packets_to_transactions_converter add wave -noupdate /sopc_system_jtag_master_tb/dut/the_jtag_master/jtag_master/readdatavalid_to_the_altera_jtag_avalon_master_packets_to_transactions_converter add wave -noupdate -divider {LED PIO}  

 

When I compare the bfm simulation and this jtag simulation they are comparable. See also the attached modelsim files of the jtag simulation. It shows the complete names as well as the values. 

 

Your hint to look at the VTAP location points me in the exact location to see the similar picture of figure 7 on page 18 of your document, for quartus 10.1. Thanks for that.  

However...sorry for being such a newbie... I'm missing the point your are trying to make in par 3.5.3. on page 17 and the figure on page 18. I try to understand the text, but this is higher science for me.  

 

Rgds, 

Kimberley
Altera_Forum
Honored Contributor I
367 Views

 

--- Quote Start ---  

 

Your hint to look at the VTAP location points me in the exact location to see the similar picture of figure 7 on page 18 of your document, for quartus 10.1. Thanks for that.  

 

--- Quote End ---  

You're welcome. 

 

 

--- Quote Start ---  

 

However...sorry for being such a newbie... I'm missing the point your are trying to make in par 3.5.3. on page 17 and the figure on page 18. I try to understand the text, but this is higher science for me.  

 

--- Quote End ---  

No need to apologize. The best way to learn is to try to understand why and how things work. 

 

The purpose of the comment at the start of that section: 

 

“Test what you fly, and fly what you test” 

 

Is that you should simulate exactly what you plan on testing in hardware. If you simulate a different IP block, than the you use in hardware (synthesize), then what's the point of your simulation? 

 

Altera recommends using a BFM for simulation, and then expects you to trust them that a completely different component, the JTAG-to-Avalon-MM bridge "Just works" - there is no official simulation support for that component. So when you test your Avalon-MM slave IP using a BFM and then synthesize hardware and use a JTAG-to-Avalon-MM bridge, although your slave IP is common, the master IP is not, so you are not testing what you fly. Your slave component might have bugs that only show up in the hardware test and not in simulation, because the masters generate different Avalon-MM transactions. 

 

The JTAG-to-Avalon-MM analysis document that the tutorial links to has a deeper analysis of that component, and there are minor errors in its design. 

 

Cheers, 

Dave
Altera_Forum
Honored Contributor I
367 Views

Hi Dave, 

 

Thanks for explaining. Now it's more clear. 

 

Rgds, 

Kimberley
Altera_Forum
Honored Contributor I
367 Views

Hi Dave, 

 

I'm trying to compile the design. And in the past I never had trouble in adding my sopc file to a quartus project. I looked at your synthese scripts but didn't use them. 

 

I get two error messages on the bfm_master and the jtag_master. 

 

--- Quote Start ---  

 

Error: Node instance "bfm_master" instantiates undefined entity "altera_avalon_mm_master_bfm" 

 

Error: Node instance "jtag_master" instantiates undefined entity "altera_jtag_avalon_master" 

[/QOUTE]I'm wondering if a specific file needs to be added to my project? 

 

See also the attached image and the qar file. 

 

Rgds, 

Kimberley
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