Tutorial: Using the USB-Blaster as an SOPC/Qsys Avalon-MM master

[Altera_Forum]

Hi all, 

 I've put together a tutorial on how to use the Altera JTAG-to-Avalon-MM master and Altera Verification IP Avalon-MM BFM Master under both SOPC builder and Qsys.  http://www.ovro.caltech.edu/~dwh/correlator/pdf/altera_jtag_to_avalon_mm_tutorial.pdf (http://www.ovro.caltech.edu/%7edwh/correlator/pdf/altera_jtag_to_avalon_mm_tutorial.pdf) http://www.ovro.caltech.edu/~dwh/correlator/pdf/altera_jtag_to_avalon_mm_tutorial.zip (http://www.ovro.caltech.edu/%7edwh/correlator/pdf/altera_jtag_to_avalon_mm_tutorial.zip)  The tutorial walks the user through the creation of an SOPC or Qsys system design, and provides scripts that automate the re-generation of the system. The tutorial shows how to simulate using Modelsim-ASE, and shows how to communicate with the hardware using System Console, quartus_stp, and then how to run a TCP/IP server under System Console or quartus_stp, and then communicate with that server from client code written in Tcl/Tk (a simple GUI) and a command-line C interface.  Let me know if you like it, or have feedback/suggestions on how to improve the document.  Cheers, Dave

[Altera_Forum]

Hi Kimberley, 

   --- Quote Start ---   I'm trying to compile the design. And in the past I never had trouble in adding my sopc file to a quartus project. I looked at your synthese scripts but didn't use them.  I get two error messages on the bfm_master and the jtag_master.  Error: Node instance "bfm_master" instantiates undefined entity "altera_avalon_mm_master_bfm"  Error: Node instance "jtag_master" instantiates undefined entity "altera_jtag_avalon_master" I'm wondering if a specific file needs to be added to my project?   --- Quote End ---    These files are listed in the .qip file. You should be able to use "Project->Add/remove files in project" to add the .qip file to the project. Try synthesizing the project after you've added the .qip.   If you still cannot get it to work, try running my synthesis script and see if that builds correctly. If it does not, let me know, and I'll install version 10.1 and see if I can figure it out.  Cheers, Dave

[Altera_Forum]

Hi Dave, 

 Adding the qip file solve the issue. It compiles now. I will start trying in what you describe in chapter 5.  Thanks again.  Best Regards, Kimberley

[Altera_Forum]

Hi Kimberley, 

  --- Quote Start ---   Adding the qip file solve the issue. It compiles now.   --- Quote End ---    Great!  Cheers, Dave

[Altera_Forum]

Hi Dave, 

 Two more questions: I got as far as page 33. The System Console session works for "figure 13", meaning all the master_write and master_read commands.  The next System Console session works for "figure 14".  Except the reading and writing of the ram. It appears that the response is overwriting other addresses as well, or the response is always the latest written value. See attached the image of System Console writing and reading to address 0 and 1, with both different values. When I re-read address 0, after I have written to address 1 as well, address 0 returns the value of address 1. I've also attached an image of my sopc system.  The second question is: How do I get the tcl prompt as in "figure 15". Or in otherwords: How do I start a quartus_stp session that gives me a tcl prompt. When I type it in a dos-prompt I don't get a tcl prompt. See also an image attached of what I got.   Rgds, Kimberleyhttps://www.alteraforum.com/forum/attachment.php?attachmentid=6444 https://www.alteraforum.com/forum/attachment.php?attachmentid=6445 https://www.alteraforum.com/forum/attachment.php?attachmentid=6446

[Altera_Forum]

Hi Kimberley, 

   --- Quote Start ---   The next System Console session works for "figure 14".  Except the reading and writing of the ram. It appears that the response is overwriting other addresses as well, or the response is always the latest written value. See attached the image of System Console writing and reading to address 0 and 1, with both different values. When I re-read address 0, after I have written to address 1 as well, address 0 returns the value of address 1. I've also attached an image of my sopc system.   --- Quote End ---    The Avalon-MM address passed to the procedure needs to be byte based, i.e., address 0 is the first address for a 32-bit write, while address 4 is the next address for a 32-bit write. Avalon-MM masters and the SOPC address map is byte-based ... sorry for not making that clearer :)    --- Quote Start ---   The second question is: How do I get the tcl prompt as in "figure 15". Or in otherwords: How do I start a quartus_stp session that gives me a tcl prompt. When I type it in a dos-prompt I don't get a tcl prompt. See also an image attached of what I got.   --- Quote End ---    quartus_stp -s  Cheers, Dave

[Altera_Forum]

Hi Dave, 

 Just to let you know I completed the the quartus_stp -s session as well. It works fine (on a monkey see, monkey do) basis. ;-)  One thing I noticed is that reading the ram on an not-times-4 address gives a different result then in System Console. The read value 'shifts around'. Why?  Rgds, Kimberleyhttps://www.alteraforum.com/forum/attachment.php?attachmentid=6450

[Altera_Forum]

Hi Kimberly, 

   --- Quote Start ---   Just to let you know I completed the the quartus_stp -s session as well. It works fine (on a monkey see, monkey do) basis. ;-)   --- Quote End ---    Excellent :)    --- Quote Start ---   One thing I noticed is that reading the ram on an not-times-4 address gives a different result then in System Console. The read value 'shifts around'. Why?   --- Quote End ---    I'm not sure what the 'exact' sequence going on in this particular case is, you could probe with SignalTap and see the transactions, but if you look carefully at the data, you'll see the value is not shifting randomly, its shifting relative to the LSB address bits, so for your write of 0x12345678 to address zero, the 32-bit little endian bytes in memory are:   byte byte address data -------- ----- 0 0x78 1 0x56 2 0x34 3 0x12   If you read from address 0, the little-endian 32-bit word you read is 0x12345678, whereas if you read from 1, 0x56 will be in the LSB position, so you should read 0x78123456, which you do. Similarly, the read address 2 should be 0x56781234, and from 3 0x34567812, and again, these are the values you read.  Note how for each read, the 4 bytes at the modulo-4-byte address (address 0 or address 4) get packed into a 32-bit word little-endian style, where the LSB byte is the byte at the address you actually read from. As you work with computers, you will find this sort of modulo operation occurs with memory caches, DDR memory bursts, and other devices.  By the way - nice work on "just trying stuff" - and then asking questions when things do not appear to make sense.  Cheers, Dave

[Altera_Forum]

Hi Kimberley, 

   --- Quote Start ---   1) Figure 16 shows a TCL/TK GUI. Is that code also in the tutorial files?   --- Quote End ---   Yes - jtag_client_server/jtag_client.tcl.    --- Quote Start ---   2) I've compiled the jtag_client.c file succesful.  I've started the server in quartus_stp. When I write to the ram as described the server replies that it's an empty packet and disconnects. Why is that? See attached image as well. 3) The same appears with System Console. My first assumption would be that's something in the C-file, as both server application respond the same. Any suggestions? See the other attached image as well too.   --- Quote End ---    Try it several times. The server will produce the same message each time a client connects.  What is happening is that when you run the command line application, a socket is opened, the client sends the command, receives the response, closes the socket, and then exits. The server is still running, and it sees the client disconnect. The server is just reporting the status of the client socket as it closes down.  Cheers, Dave

[Altera_Forum]

Hi Dave, 

 I got the client/server stuff running as well. And also the TCL/TK GUI.  I want to thank you for the very informative document and source files. It's very clear and very accurate with a lot of details.  And I also want to thank you for the help given trough this forum almost on a daily bases. This has teached me a lot, and I want to start using this into my designs as well.  Thank you very much. Best Regards, Kimberley

[Altera_Forum]

Hi Kimberley, 

  --- Quote Start ---   I got the client/server stuff running as well. And also the TCL/TK GUI.   --- Quote End ---    Excellent!    --- Quote Start ---   I want to thank you for the very informative document and source files. It's very clear and very accurate with a lot of details.  And I also want to thank you for the help given trough this forum almost on a daily bases. This has teached me a lot, and I want to start using this into my designs as well.  Thank you very much.   --- Quote End ---   You are welcome. It is always a pleasure to help someone willing to learn. Best of luck with your designs. Feel free to ask questions if you get stuck.  Cheers, Dave

[Altera_Forum]

Hi Dave, 

 First of all, thank you for putting this tutorial together. It's very well written and it's been a great resource.   Unfortunately for me, I'm having some issues getting the jtag-to-Avalon-MM bridge to work on a Altera Stratix IV dev board, 530 edition. I'm able to get everything to compile, and everything passes in simulation. However, after programming the FPGA, and using quartus_stp to issue commands from Figure 15, I get the following error: tcl> jtag_write 0 0 0x23 Error: incorrect number of response bytes!   Everything up to that point works. The jtag_open, jtag_print_hub_info and jtag_print_node_info all produce the expected result.  Do you have any ideas what could be going on here?  I should mention that I've modified the design a bit by dropping the button and LED PIOs, and moving the on chip RAM to address 0. But I've updated the scripts accordingly, and this modified version passes in simulation.  Anyways, if you have any pointers, I'd be grateful.  Thanks in advance, Omid

[Altera_Forum]

--- Quote Start ---   First of all, thank you for putting this tutorial together. It's very well written and it's been a great resource.    --- Quote End ---   You're welcome.    --- Quote Start ---   Unfortunately for me, I'm having some issues getting the jtag-to-Avalon-MM bridge to work on a Altera Stratix IV dev board, 530 edition. I'm able to get everything to compile, and everything passes in simulation. However, after programming the FPGA, and using quartus_stp to issue commands from Figure 15, I get the following error:tcl> jtag_write 0 0 0x23 Error: incorrect number of response bytes!   Everything up to that point works. The jtag_open, jtag_print_hub_info and jtag_print_node_info all produce the expected result.  Do you have any ideas what could be going on here?   --- Quote End ---    Any reason why you're using quartus_stp? If you are just using the command line, then SystemConsole works fine. I was using it today on the 230K version of the same board.  I won't be at work tomorrow, but I'll see if I can find the issue with quartus_stp on Friday.  For now, why not try using SystemConsole - look at the jtag_cmds_sc.tcl scripts in the boards area.  Which version of Quartus are you using?  Cheers, Dave

[Altera_Forum]

I don't have a good reason not to use SystemConsole. And so I just tried it, and works like a charm :) 

 For the sake of others who may wonder, I tried both Quartus 11.1sp1 and 12.0sp2. Both worked equally well.  Thanks for the help!  Omid

[Altera_Forum]

Very useful tutorial! 

Thank you very much.  M.

[Altera_Forum]

Hi Dave, 

 How come that System Console and quartus_stp are so slow? To write the online ram from 0 to 3FF, takes about 27 seconds. Is there a way to speed this up? Or is this because of how System Console and quartus_stp are written?  For comparison, a competitor vendor of PLDs does the same in less then 1 second.  Rgds, Kimberley

[Altera_Forum]

Hi Kimberley, 

   --- Quote Start ---   How come that System Console and quartus_stp are so slow?   --- Quote End ---   If you look in the JTAG-to-Avalon-MM/ST analysis document ...  http://www.ovro.caltech.edu/~dwh/correlator/pdf/altera_jtag_to_avalon_analysis.pdf  You will see that the JTAG interface uses a 6MHz clock, and 8-bit byte-mode transfers occur in about 10 clocks, i.e., the best data rate you can achieve is about 600kbits/s.  The master_read/write_8/16/32 Tcl procedures only transfer one item of data at a time. Higher performance is achieved using master_read/write_memory routines. To use those Tcl procedures, you need to split your read write data into lists of bytes.  Try modifying your code to use those Tcl procedures. If you cannot get it to work, let me know, and I'll write some test routines for you.  Cheers, Dave

[Altera_Forum]

--- Quote Start ---   The master_read/write_8/16/32 Tcl procedures only transfer one item of data at a time. Higher performance is achieved using master_read/write_memory routines. To use those Tcl procedures, you need to split your read write data into lists of bytes. Try modifying your code to use those Tcl procedures.   --- Quote End ---    Hi Dave,  I did modify the code and it works super with master_write_memory. Thanks again, your a great help.  Rgds, Kimberley

[Altera_Forum]

--- Quote Start ---   I did modify the code and it works super with master_write_memory.   --- Quote End ---    Awesome :)  Cheers, Dave

[Altera_Forum]

--- Quote Start ---  How come that System Console and quartus_stp are so slow?  --- Quote End ---    If you're using a recent version of ACDS then SystemConsole provides the master_write_from_file command which is even faster (providing you have your data available as a binary file)

[Altera_Forum]

Hi wombat, 

  --- Quote Start ---  If you're using a recent version of ACDS then SystemConsole provides the master_write_from_file command which is even faster (providing you have your data available as a binary file)  --- Quote End ---    Thanks! When was this function introduced (which Quartus release?)?  I doubt that it will be faster at the JTAG layer (since the JTAG traces show that master_read/write_memory are as efficient as possible), but at least it saves Tcl performing binary->string and string->binary conversions.  Cheers, Dave

[Altera_Forum]

Hi Dave, 

 I have a question; Say I take your example design with the ram, leds and buttons, and instead of buttons I use switches. I run this design on two boards. On one board I put the switch to high / one, meaning Master. On the other board I put the switch to low/zero, meaning Slave.   I connect two usb-byteblaster to my pc and start System Console Situation 1: How do I: - Scan for all available jtag2avalon master? - How do I assign a tcl variable MASTER, to the board that has the switch to one? So that I can use that MASTER in my other procedures for doing master_functions. For example "lit led 0 if you are a master board" - And the same question for the slave.   Situation 2: This should be dynamic. When I have this running, I want to be able to switch both boards in the other mode. Meaning, the master becomes slave, and the slave becomes master. I would like to run the same script without modifying it, and detect the new master and new slave board. Is that possible?   Situation 3: Now I start debugging, and add sometimes a NIOS with a jtag_uart, sometimes signaltap, sometimes both and sometimes none. Can this script then still identify the jtag2avalon master and detect the master board and the slave board? I assume that the nios has certain "jtag_identifier_code", and the signaltap as well.   Rgds, Kimberley