FIR Coeff Storage in CycloneIII

[Altera_Forum]

Hello 

 I'm using a CycloneIII to implement a Fir Filter. I would like to dynamically adjust the coefficients, so I'm trying to use the coefficient reload function. The problem is that the megafunction doesn't seem to be optimized to use the M9Ks available in CycloneIII, it stores the coefficients in blocks of 4Kbits, so half of the M9K is wasted. That being the case, I'm unable to fit my design on the FPGA. Another problem is that I need two parallel Fir Filters, but as they use the same coefficient set so it would be possible to use the same blocks of M9Ks to feed both filters (instead of duplicating). Quartus doesn't optimize that too and allocates RAM independently for each filter. Can I force him to use the same RAM? I know that I could use only one dual channel filter to help in this case, but it would be necessary to double the clock rate of the filter and it is very high already In the end, with these two problems my design requires 70M9Ks when only 18M9Ks would be sufficient.  Thanks a lot  Thiago

[Altera_Forum]

Hello, 

 I don't know about all FIR core features, but I guess, the incomplete usage of RAM blocks could have a systematic reason, cause Altera generally doesn't waste resources this way, athough it may seem so at first look. Could it be, that prescribed by filter operating frequency multiple parameters must be accessed simultanously? This won't work without multiplying the RAM block usage.  Regards, Frank

[Altera_Forum]

Hmm, I get your point. 

The thing that makes me believe that it isn't optimizing well is that if I switch the FIR to CycloneII that has M4Ks only, the amount of memory blocks used remains the same. 35M9Ks (CycloneIII) or 35M4Ks (CycloneII) per filter. The same happens if we compare StratixII with M4Ks and StratixIII with M9Ks. You could check that by trying to instantiate a Fir Filter and switch between the devices to see the resource allocation.  Thanks! Thiago

[Altera_Forum]

I think FvM probably hit it on the head. Coefficients in FIR filters are usually required on every clock cycle, so the number of ram blocks required would be directly related to the number of "real" taps in the design.  

 Since FIRs can use symmetry, the number of "real" taps or mulitpliers, may not equal the number of filter taps in the system.  IE you can get a 128 tap decimating filter with 4 real taps, but you would require memory elements between taps, and for each coefficient, so it would probably be 4 + 7 ram blocks used. It would not be able to share these ram blocks even though they would be very small in actual number of bits used.  The number of ram blocks actually used will vary significantly depending on your setup of the filter.