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Valued Contributor III
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FIR compiler II syntax error

I am using quartus 15.1 to generate a fir ii core. I chose the verilog option for the cores language. 

 

I am using candace tools to elaborate and simulate a design with the generated FIR II core.  

Here are the options I am using when I elaborate and simulate my design  

irun: 14.10-s021: (c) Copyright 1995-2015 Cadence Design Systems, Inc. 

TOOL: irun 14.10-s021: Started on Jun 23, 2016 at 16:49:19 EDT 

irun 

-cdslib cds.lib 

-hdlvar hdl.var 

-access +c 

-smartorder 

-status 

-v93 

-work worklib 

-input scripts/tb_tx_filters.tcl 

-top tb_tx_filters 

-vlogext .vo,.VO,.vp,.VP 

-vhdlext .vho,.VHO 

-nostdout 

-clean 

-l logs/irun.log 

-makelib shlslib 

 

 

During the elaboration phase I get the following error../../../../ip_cores/core_files/fir_interpolate8/fir_interpolate8_sim/auk_dspip_roundsat_hpfir.vhd: 

max_val <= (IN_WIDTH_g-REM_LSB_BIT_g-REM_MSB_BIT_g-1 => '0', others => '1'); 

ncvhdl_p: *E,AGNLSC (../../../../ip_cores/core_files/fir_interpolate8/fir_interpolate8_sim/auk_dspip_roundsat_hpfir.vhd,143|54): non-locally static or null range choice must be only choice [7.3.2.2]. 

max_val <= (IN_WIDTH_g-REM_LSB_BIT_g-REM_MSB_BIT_g-1 => '0', others => '1'); 

ncvhdl_p: *E,AGNLSC (../../../../ip_cores/core_files/fir_interpolate8/fir_interpolate8_sim/auk_dspip_roundsat_hpfir.vhd,143|70): non-locally static or null range choice must be only choice [7.3.2.2]. 

min_val <= (IN_WIDTH_g-REM_LSB_BIT_g-REM_MSB_BIT_g-1 => '1', others => '0'); 

ncvhdl_p: *E,AGNLSC (../../../../ip_cores/core_files/fir_interpolate8/fir_interpolate8_sim/auk_dspip_roundsat_hpfir.vhd,144|54): non-locally static or null range choice must be only choice [7.3.2.2]. 

min_val <= (IN_WIDTH_g-REM_LSB_BIT_g-REM_MSB_BIT_g-1 => '1', others => '0'); 

ncvhdl_p: *E,AGNLSC (../../../../ip_cores/core_files/fir_interpolate8/fir_interpolate8_sim/auk_dspip_roundsat_hpfir.vhd,144|70): non-locally static or null range choice must be only choice [7.3.2.2]. 

errors: 4, warnings: 0 

 

 

This is the section of the file auk_dspip_roundsat_hpfir.vhd causing the error.  

----------------------------------------------------------------------------- 

-- msb : trunc/saturation 

----------------------------------------------------------------------------- 

remove_msb: if REM_MSB_BIT_g > 0 generate 

signal min_val, max_val : std_logic_vector(IN_WIDTH_g-REM_LSB_BIT_g-REM_MSB_BIT_g-1 downto 0); 

begin 

trunc_msb: if REM_MSB_TYPE_g = "trunc" generate 

begin 

data_msb <= data_lsb(IN_WIDTH_g-REM_LSB_BIT_g-REM_MSB_BIT_g-1 downto 0); 

dataout <= data_msb; 

valid <= valid_lsb; 

end generate trunc_msb; 

 

 

sat_msb: if REM_MSB_TYPE_g = "sat" generate 

max_val <= (IN_WIDTH_g-REM_LSB_BIT_g-REM_MSB_BIT_g-1 => '0', others => '1'); 

min_val <= (IN_WIDTH_g-REM_LSB_BIT_g-REM_MSB_BIT_g-1 => '1', others => '0'); 

data_msb <= std_logic_vector(max_val) when signed(data_lsb) > signed(max_val) else 

std_logic_vector(min_val) when signed(data_lsb) < signed(min_val) else 

data_lsb(IN_WIDTH_g-REM_LSB_BIT_g-REM_MSB_BIT_g-1 downto 0); 

msb_p : process (clk, reset_n) 

begin 

if reset_n = '0' then 

dataout <= (others => '0'); 

valid <= '0'; 

elsif rising_edge(clk) then 

if valid_lsb = '1' then 

dataout <= data_msb; 

end if; 

valid <= valid_lsb; 

end if; 

end process msb_p; 

end generate sat_msb;  

end generate remove_msb; 

 

 

how can i resolve these errors so my design will elaborate the fir ii core?
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