FIR filter design with IEEE 754 half-precision floating point

[Altera_Forum]

Hi All 

 We are in the initial phase of a project which implements processing of biomedical signals. I am trying to implement FIR filter with IEEE 754 half-precision (16-bit) floating point arithmetic.  Please find my doubts below,  1. Major doubt is that, WILL the data format from the ADC to the FPGA (through I2C interface) be different from the data format which I try to implement?  OR any of you knows an ADC chip which produces the specific data format?  2. If I am not able to get an ADC which produces the specific data format, I would need to convert the format. Is this the way that is normally followed in FPGA implementations? (Sorry, I am new to FPGA implementations)  3. I decided to use this format since the biomedical signals are in the range (+/-1mV , after amplification). Please correct me if am totally wrong.  Thanks a lot for your replies.

[Altera_Forum]

No ADC uses floating point format, also it's usage for signal processing is questionable. 16 up to 24 bit fixed point format seems to be more suitable. 

 Data width is a matter of signal dynamic (signal to noise ratio), not absolute signal level. Low level signal have most likely smaller signal to noise ratio and don't have so much significant bits.

[Altera_Forum]

--- Quote Start ---  No ADC uses floating point format, also it's usage for signal processing is questionable. 16 up to 24 bit fixed point format seems to be more suitable.  Data width is a matter of signal dynamic (signal to noise ratio), not absolute signal level. Low level signal have most likely smaller signal to noise ratio and don't have so much significant bits.  --- Quote End ---    Thanks for the quick response.   If I am going with fixed point, I have another quick question regarding rounding of 32-bit to 16-bit after fixed-point multiplication of two 16-bit numbers. Could you please give some insight into this? Let us assume, I am assigning MSB for Sign bit, 4 bits significant and 11 bits for fractional (any IEEE standard for this?)  Thanks a lot.

[Altera_Forum]

You want to look at fractional integer formats. Go through these slides: 

 http://www.ovro.caltech.edu/~dwh/correlator/pdf/esc-111paper_hawkins.pdf http://www.ovro.caltech.edu/~dwh/correlator/pdf/esc-111slides_hawkins.pdf  and source  http://www.ovro.caltech.edu/~dwh/correlator/pdf/esc2011_fpga_dsp_code.zip  You'll want to look at using convergent rounding, there's code in that zip.  If you're testing FIR filters, then you can use an LFSR as a digital noise source:  http://www.ovro.caltech.edu/~dwh/correlator/pdf/lfsr_tutorial.pdf http://www.ovro.caltech.edu/~dwh/correlator/pdf/lfsr_tutorial_src.zip  Cheers, Dave

[Altera_Forum]

As an additional comment, all required rounding/truncation/saturation operation are handled in the IEEE fixed point package. 

 A convenient way to implement FIR filters that take advantage of the FPGA hardware is to use the Altera FIR compiler.

[Altera_Forum]

Thanks a lot Dave!!! 

Will go through the pdf and the code :-)

[Altera_Forum]

Per FvM's comment: 

  --- Quote Start ---  As an additional comment, all required rounding/truncation/saturation operation are handled in the IEEE fixed point package.   --- Quote End ---    There's an example zip file (vhdl_fixed_pkg_example.zip) in this thread:  http://www.alteraforum.com/forum/showthread.php?t=37555&page=6    --- Quote Start ---   A convenient way to implement FIR filters that take advantage of the FPGA hardware is to use the Altera FIR compiler.  --- Quote End ---    This is also a good point. The FIR filter example in the zip example I created to match the example delivered with the BeMicro-SDK, but with more flexibility. Altera's FIR tool will generate a more optimal FIR given that 'optimal' depends on the technology. The slides linked above have more comments (and images) on this.  Cheers, Dave